| j721e-evm.c (78d2a05ef22e7b5863b01e073dd6a06b3979bb00) | j721e-evm.c (82d28b67f780910f816fe1cfb0f676fc38c4cbb3) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/module.h> --- 183 unchanged lines hidden (view full) --- 192 } 193 194 if (ret) { 195 dev_err(priv->dev, "No valid clock configuration for %u Hz\n", 196 rate); 197 return ret; 198 } 199 | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/module.h> --- 183 unchanged lines hidden (view full) --- 192 } 193 194 if (ret) { 195 dev_err(priv->dev, "No valid clock configuration for %u Hz\n", 196 rate); 197 return ret; 198 } 199 |
| 200 if (priv->hsdiv_rates[domain->parent_clk_id] != scki) { | 200 if (domain->parent_clk_id == -1 || priv->hsdiv_rates[domain->parent_clk_id] != scki) { |
| 201 dev_dbg(priv->dev, 202 "%s configuration for %u Hz: %s, %dxFS (SCKI: %u Hz)\n", 203 audio_domain == J721E_AUDIO_DOMAIN_CPB ? "CPB" : "IVI", 204 rate, 205 clk_id == J721E_CLK_PARENT_48000 ? "PLL4" : "PLL15", 206 ratios_for_pcm3168a[i], scki); 207 208 if (domain->parent_clk_id != clk_id) { --- 705 unchanged lines hidden --- | 201 dev_dbg(priv->dev, 202 "%s configuration for %u Hz: %s, %dxFS (SCKI: %u Hz)\n", 203 audio_domain == J721E_AUDIO_DOMAIN_CPB ? "CPB" : "IVI", 204 rate, 205 clk_id == J721E_CLK_PARENT_48000 ? "PLL4" : "PLL15", 206 ratios_for_pcm3168a[i], scki); 207 208 if (domain->parent_clk_id != clk_id) { --- 705 unchanged lines hidden --- |