acp.h (2f98e686ef59b5d19af5847d755798e2031bee3a) acp.h (1a74b21ce59f4343e8bf64ec4c20bcbbaea96c5f)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>

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56#define ACP_DSP_TO_HOST_IRQ 0x04
57
58#define ACP_RN_PCI_ID 0x01
59#define ACP_RMB_PCI_ID 0x6F
60
61#define HOST_BRIDGE_CZN 0x1630
62#define HOST_BRIDGE_RMB 0x14B5
63#define ACP_SHA_STAT 0x8000
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>

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56#define ACP_DSP_TO_HOST_IRQ 0x04
57
58#define ACP_RN_PCI_ID 0x01
59#define ACP_RMB_PCI_ID 0x6F
60
61#define HOST_BRIDGE_CZN 0x1630
62#define HOST_BRIDGE_RMB 0x14B5
63#define ACP_SHA_STAT 0x8000
64#define ACP_PSP_TIMEOUT_COUNTER 5
64#define ACP_PSP_TIMEOUT_US 1000000
65#define ACP_EXT_INTR_ERROR_STAT 0x20000000
66#define MP0_C2PMSG_114_REG 0x3810AC8
67#define MP0_C2PMSG_73_REG 0x3810A24
68#define MBOX_ACP_SHA_DMA_COMMAND 0x70000
65#define ACP_EXT_INTR_ERROR_STAT 0x20000000
66#define MP0_C2PMSG_114_REG 0x3810AC8
67#define MP0_C2PMSG_73_REG 0x3810A24
68#define MBOX_ACP_SHA_DMA_COMMAND 0x70000
69#define MBOX_DELAY 1000
69#define MBOX_DELAY_US 1000
70#define MBOX_READY_MASK 0x80000000
71#define MBOX_STATUS_MASK 0xFFFF
72
73#define BOX_SIZE_512 0x200
74#define BOX_SIZE_1024 0x400
75
76#define EXCEPT_MAX_HDR_SIZE 0x400
77#define AMD_STACK_DUMP_SIZE 32
78
79#define SRAM1_SIZE 0x13A000
70#define MBOX_READY_MASK 0x80000000
71#define MBOX_STATUS_MASK 0xFFFF
72
73#define BOX_SIZE_512 0x200
74#define BOX_SIZE_1024 0x400
75
76#define EXCEPT_MAX_HDR_SIZE 0x400
77#define AMD_STACK_DUMP_SIZE 32
78
79#define SRAM1_SIZE 0x13A000
80#define PROBE_STATUS_BIT BIT(31)
80
81enum clock_source {
82 ACP_CLOCK_96M = 0,
83 ACP_CLOCK_48M,
84 ACP_CLOCK_24M,
85 ACP_CLOCK_ACLK,
86 ACP_CLOCK_MCLK,
87};

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151 struct snd_sof_dev *sdev;
152 struct snd_pcm_substream *substream;
153 struct snd_dma_buffer *dmab;
154 int num_pages;
155 int stream_tag;
156 int active;
157 unsigned int reg_offset;
158 size_t posn_offset;
81
82enum clock_source {
83 ACP_CLOCK_96M = 0,
84 ACP_CLOCK_48M,
85 ACP_CLOCK_24M,
86 ACP_CLOCK_ACLK,
87 ACP_CLOCK_MCLK,
88};

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152 struct snd_sof_dev *sdev;
153 struct snd_pcm_substream *substream;
154 struct snd_dma_buffer *dmab;
155 int num_pages;
156 int stream_tag;
157 int active;
158 unsigned int reg_offset;
159 size_t posn_offset;
160 struct snd_compr_stream *cstream;
161 u64 cstream_posn;
159};
160
161struct sof_amd_acp_desc {
162 unsigned int rev;
163 unsigned int host_bridge_id;
164 u32 pgfsm_base;
165 u32 ext_intr_stat;
166 u32 dsp_intr_base;
167 u32 sram_pte_offset;
168 u32 hw_semaphore_offset;
169 u32 acp_clkmux_sel;
170 u32 fusion_dsp_offset;
162};
163
164struct sof_amd_acp_desc {
165 unsigned int rev;
166 unsigned int host_bridge_id;
167 u32 pgfsm_base;
168 u32 ext_intr_stat;
169 u32 dsp_intr_base;
170 u32 sram_pte_offset;
171 u32 hw_semaphore_offset;
172 u32 acp_clkmux_sel;
173 u32 fusion_dsp_offset;
174 u32 probe_reg_offset;
171};
172
173/* Common device data struct for ACP devices */
174struct acp_dev_data {
175 struct snd_sof_dev *dev;
176 /* DMIC device */
177 struct platform_device *dmic_dev;
178 unsigned int fw_bin_size;
179 unsigned int fw_data_bin_size;
180 u32 fw_bin_page_count;
181 dma_addr_t sha_dma_addr;
182 u8 *bin_buf;
183 dma_addr_t dma_addr;
184 u8 *data_buf;
185 struct dma_descriptor dscr_info[ACP_MAX_DESC];
186 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
187 struct acp_dsp_stream *dtrace_stream;
188 struct pci_dev *smn_dev;
175};
176
177/* Common device data struct for ACP devices */
178struct acp_dev_data {
179 struct snd_sof_dev *dev;
180 /* DMIC device */
181 struct platform_device *dmic_dev;
182 unsigned int fw_bin_size;
183 unsigned int fw_data_bin_size;
184 u32 fw_bin_page_count;
185 dma_addr_t sha_dma_addr;
186 u8 *bin_buf;
187 dma_addr_t dma_addr;
188 u8 *data_buf;
189 struct dma_descriptor dscr_info[ACP_MAX_DESC];
190 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
191 struct acp_dsp_stream *dtrace_stream;
192 struct pci_dev *smn_dev;
193 struct acp_dsp_stream *probe_stream;
189};
190
191void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
192void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
193
194int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
195int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
196 unsigned int dest_addr, int dsp_data_size);

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268void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags);
269
270static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
271{
272 const struct sof_dev_desc *desc = pdata->desc;
273
274 return desc->chip_info;
275}
194};
195
196void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
197void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
198
199int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
200int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
201 unsigned int dest_addr, int dsp_data_size);

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273void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags);
274
275static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
276{
277 const struct sof_dev_desc *desc = pdata->desc;
278
279 return desc->chip_info;
280}
281
282int acp_probes_register(struct snd_sof_dev *sdev);
283void acp_probes_unregister(struct snd_sof_dev *sdev);
284
276#endif
285#endif