axg-fifo.c (df7686101956929dcea410971656e34926773b88) axg-fifo.c (7c02509a8a9981fb2c16b75904423e7ab2f9f43a)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright (c) 2018 BayLibre, SAS.
4// Author: Jerome Brunet <jbrunet@baylibre.com>
5
6#include <linux/clk.h>
7#include <linux/of_irq.h>
8#include <linux/of_platform.h>

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14#include <sound/soc-dai.h>
15
16#include "axg-fifo.h"
17
18/*
19 * This file implements the platform operations common to the playback and
20 * capture frontend DAI. The logic behind this two types of fifo is very
21 * similar but some difference exist.
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright (c) 2018 BayLibre, SAS.
4// Author: Jerome Brunet <jbrunet@baylibre.com>
5
6#include <linux/clk.h>
7#include <linux/of_irq.h>
8#include <linux/of_platform.h>

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14#include <sound/soc-dai.h>
15
16#include "axg-fifo.h"
17
18/*
19 * This file implements the platform operations common to the playback and
20 * capture frontend DAI. The logic behind this two types of fifo is very
21 * similar but some difference exist.
22 * These differences the respective DAI drivers
22 * These differences are handled in the respective DAI drivers
23 */
24
25static struct snd_pcm_hardware axg_fifo_hw = {
26 .info = (SNDRV_PCM_INFO_INTERLEAVED |
27 SNDRV_PCM_INFO_MMAP |
28 SNDRV_PCM_INFO_MMAP_VALID |
29 SNDRV_PCM_INFO_BLOCK_TRANSFER |
30 SNDRV_PCM_INFO_PAUSE),

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128 /* Enable block count irq */
129 regmap_update_bits(fifo->map, FIFO_CTRL0,
130 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
131 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
132
133 return 0;
134}
135
23 */
24
25static struct snd_pcm_hardware axg_fifo_hw = {
26 .info = (SNDRV_PCM_INFO_INTERLEAVED |
27 SNDRV_PCM_INFO_MMAP |
28 SNDRV_PCM_INFO_MMAP_VALID |
29 SNDRV_PCM_INFO_BLOCK_TRANSFER |
30 SNDRV_PCM_INFO_PAUSE),

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128 /* Enable block count irq */
129 regmap_update_bits(fifo->map, FIFO_CTRL0,
130 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
131 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
132
133 return 0;
134}
135
136static int g12a_fifo_pcm_hw_params(struct snd_pcm_substream *ss,
137 struct snd_pcm_hw_params *params)
138{
139 struct axg_fifo *fifo = axg_fifo_data(ss);
140 struct snd_pcm_runtime *runtime = ss->runtime;
141 int ret;
142
143 ret = axg_fifo_pcm_hw_params(ss, params);
144 if (ret)
145 return ret;
146
147 /* Set the initial memory address of the DMA */
148 regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);
149
150 return 0;
151}
152
136static int axg_fifo_pcm_hw_free(struct snd_pcm_substream *ss)
137{
138 struct axg_fifo *fifo = axg_fifo_data(ss);
139
140 /* Disable the block count irq */
141 regmap_update_bits(fifo->map, FIFO_CTRL0,
142 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
143

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257 .ioctl = snd_pcm_lib_ioctl,
258 .hw_params = axg_fifo_pcm_hw_params,
259 .hw_free = axg_fifo_pcm_hw_free,
260 .pointer = axg_fifo_pcm_pointer,
261 .trigger = axg_fifo_pcm_trigger,
262};
263EXPORT_SYMBOL_GPL(axg_fifo_pcm_ops);
264
153static int axg_fifo_pcm_hw_free(struct snd_pcm_substream *ss)
154{
155 struct axg_fifo *fifo = axg_fifo_data(ss);
156
157 /* Disable the block count irq */
158 regmap_update_bits(fifo->map, FIFO_CTRL0,
159 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
160

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274 .ioctl = snd_pcm_lib_ioctl,
275 .hw_params = axg_fifo_pcm_hw_params,
276 .hw_free = axg_fifo_pcm_hw_free,
277 .pointer = axg_fifo_pcm_pointer,
278 .trigger = axg_fifo_pcm_trigger,
279};
280EXPORT_SYMBOL_GPL(axg_fifo_pcm_ops);
281
282const struct snd_pcm_ops g12a_fifo_pcm_ops = {
283 .open = axg_fifo_pcm_open,
284 .close = axg_fifo_pcm_close,
285 .ioctl = snd_pcm_lib_ioctl,
286 .hw_params = g12a_fifo_pcm_hw_params,
287 .hw_free = axg_fifo_pcm_hw_free,
288 .pointer = axg_fifo_pcm_pointer,
289 .trigger = axg_fifo_pcm_trigger,
290};
291EXPORT_SYMBOL_GPL(g12a_fifo_pcm_ops);
292
265int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
266{
267 struct snd_card *card = rtd->card->snd_card;
268 size_t size = axg_fifo_hw.buffer_bytes_max;
269
270 snd_pcm_lib_preallocate_pages(rtd->pcm->streams[type].substream,
271 SNDRV_DMA_TYPE_DEV, card->dev,
272 size, size);
273 return 0;
274}
275EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
276
277static const struct regmap_config axg_fifo_regmap_cfg = {
278 .reg_bits = 32,
279 .val_bits = 32,
280 .reg_stride = 4,
293int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
294{
295 struct snd_card *card = rtd->card->snd_card;
296 size_t size = axg_fifo_hw.buffer_bytes_max;
297
298 snd_pcm_lib_preallocate_pages(rtd->pcm->streams[type].substream,
299 SNDRV_DMA_TYPE_DEV, card->dev,
300 size, size);
301 return 0;
302}
303EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
304
305static const struct regmap_config axg_fifo_regmap_cfg = {
306 .reg_bits = 32,
307 .val_bits = 32,
308 .reg_stride = 4,
281 .max_register = FIFO_STATUS2,
309 .max_register = FIFO_INIT_ADDR,
282};
283
284int axg_fifo_probe(struct platform_device *pdev)
285{
286 struct device *dev = &pdev->dev;
287 const struct axg_fifo_match_data *data;
288 struct axg_fifo *fifo;
289 struct resource *res;

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334 return fifo->irq;
335 }
336
337 return devm_snd_soc_register_component(dev, data->component_drv,
338 data->dai_drv, 1);
339}
340EXPORT_SYMBOL_GPL(axg_fifo_probe);
341
310};
311
312int axg_fifo_probe(struct platform_device *pdev)
313{
314 struct device *dev = &pdev->dev;
315 const struct axg_fifo_match_data *data;
316 struct axg_fifo *fifo;
317 struct resource *res;

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362 return fifo->irq;
363 }
364
365 return devm_snd_soc_register_component(dev, data->component_drv,
366 data->dai_drv, 1);
367}
368EXPORT_SYMBOL_GPL(axg_fifo_probe);
369
342MODULE_DESCRIPTION("Amlogic AXG fifo driver");
370MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");
343MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
344MODULE_LICENSE("GPL v2");
371MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
372MODULE_LICENSE("GPL v2");