rt5645.h (a3ae255e3729c1bb4507412ea29be804f703d44c) rt5645.h (79080a8b42a08fb68a1ea2e036e54a4749edbd43)
1/*
2 * rt5645.h -- RT5645 ALSA SoC audio driver
3 *
4 * Copyright 2013 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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1115#define RT5645_DMIC_1_M_SFT 9
1116#define RT5645_DMIC_1_M_NOR (0x0 << 9)
1117#define RT5645_DMIC_1_M_ASYN (0x1 << 9)
1118#define RT5645_DMIC_2_M_MASK (0x1 << 8)
1119#define RT5645_DMIC_2_M_SFT 8
1120#define RT5645_DMIC_2_M_NOR (0x0 << 8)
1121#define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1122
1/*
2 * rt5645.h -- RT5645 ALSA SoC audio driver
3 *
4 * Copyright 2013 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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1115#define RT5645_DMIC_1_M_SFT 9
1116#define RT5645_DMIC_1_M_NOR (0x0 << 9)
1117#define RT5645_DMIC_1_M_ASYN (0x1 << 9)
1118#define RT5645_DMIC_2_M_MASK (0x1 << 8)
1119#define RT5645_DMIC_2_M_SFT 8
1120#define RT5645_DMIC_2_M_NOR (0x0 << 8)
1121#define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1122
1123/* ASRC clock source selection (0x84, 0x85) */
1124#define RT5645_CLK_SEL_SYS (0x0)
1125#define RT5645_CLK_SEL_I2S1_ASRC (0x1)
1126#define RT5645_CLK_SEL_I2S2_ASRC (0x2)
1127#define RT5645_CLK_SEL_SYS2 (0x5)
1128
1123/* ASRC Control 2 (0x84) */
1129/* ASRC Control 2 (0x84) */
1124#define RT5645_MDA_L_M_MASK (0x1 << 15)
1125#define RT5645_MDA_L_M_SFT 15
1126#define RT5645_MDA_L_M_NOR (0x0 << 15)
1127#define RT5645_MDA_L_M_ASYN (0x1 << 15)
1128#define RT5645_MDA_R_M_MASK (0x1 << 14)
1129#define RT5645_MDA_R_M_SFT 14
1130#define RT5645_MDA_R_M_NOR (0x0 << 14)
1131#define RT5645_MDA_R_M_ASYN (0x1 << 14)
1132#define RT5645_MAD_L_M_MASK (0x1 << 13)
1133#define RT5645_MAD_L_M_SFT 13
1134#define RT5645_MAD_L_M_NOR (0x0 << 13)
1135#define RT5645_MAD_L_M_ASYN (0x1 << 13)
1136#define RT5645_MAD_R_M_MASK (0x1 << 12)
1137#define RT5645_MAD_R_M_SFT 12
1138#define RT5645_MAD_R_M_NOR (0x0 << 12)
1139#define RT5645_MAD_R_M_ASYN (0x1 << 12)
1140#define RT5645_ADC_M_MASK (0x1 << 11)
1141#define RT5645_ADC_M_SFT 11
1142#define RT5645_ADC_M_NOR (0x0 << 11)
1143#define RT5645_ADC_M_ASYN (0x1 << 11)
1144#define RT5645_STO_DAC_M_MASK (0x1 << 5)
1145#define RT5645_STO_DAC_M_SFT 5
1146#define RT5645_STO_DAC_M_NOR (0x0 << 5)
1147#define RT5645_STO_DAC_M_ASYN (0x1 << 5)
1148#define RT5645_I2S1_R_D_MASK (0x1 << 4)
1149#define RT5645_I2S1_R_D_SFT 4
1150#define RT5645_I2S1_R_D_DIS (0x0 << 4)
1151#define RT5645_I2S1_R_D_EN (0x1 << 4)
1152#define RT5645_I2S2_R_D_MASK (0x1 << 3)
1153#define RT5645_I2S2_R_D_SFT 3
1154#define RT5645_I2S2_R_D_DIS (0x0 << 3)
1155#define RT5645_I2S2_R_D_EN (0x1 << 3)
1156#define RT5645_PRE_SCLK_MASK (0x3)
1157#define RT5645_PRE_SCLK_SFT 0
1158#define RT5645_PRE_SCLK_512 (0x0)
1159#define RT5645_PRE_SCLK_1024 (0x1)
1160#define RT5645_PRE_SCLK_2048 (0x2)
1130#define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12)
1131#define RT5645_DA_STO_CLK_SEL_SFT 12
1132#define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8)
1133#define RT5645_DA_MONOL_CLK_SEL_SFT 8
1134#define RT5645_DA_MONOR_CLK_SEL_MASK (0xf << 4)
1135#define RT5645_DA_MONOR_CLK_SEL_SFT 4
1136#define RT5645_AD_STO1_CLK_SEL_MASK (0xf << 0)
1137#define RT5645_AD_STO1_CLK_SEL_SFT 0
1161
1162/* ASRC Control 3 (0x85) */
1138
1139/* ASRC Control 3 (0x85) */
1163#define RT5645_I2S1_RATE_MASK (0xf << 12)
1164#define RT5645_I2S1_RATE_SFT 12
1165#define RT5645_I2S2_RATE_MASK (0xf << 8)
1166#define RT5645_I2S2_RATE_SFT 8
1140#define RT5645_AD_MONOL_CLK_SEL_MASK (0xf << 4)
1141#define RT5645_AD_MONOL_CLK_SEL_SFT 4
1142#define RT5645_AD_MONOR_CLK_SEL_MASK (0xf << 0)
1143#define RT5645_AD_MONOR_CLK_SEL_SFT 0
1167
1168/* ASRC Control 4 (0x89) */
1169#define RT5645_I2S1_PD_MASK (0x7 << 12)
1170#define RT5645_I2S1_PD_SFT 12
1171#define RT5645_I2S2_PD_MASK (0x7 << 8)
1172#define RT5645_I2S2_PD_SFT 8
1173
1174/* HPOUT Over Current Detection (0x8b) */

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2184 RT5645_DMIC_DATA_GPIO11,
2185};
2186
2187enum {
2188 CODEC_TYPE_RT5645,
2189 CODEC_TYPE_RT5650,
2190};
2191
1144
1145/* ASRC Control 4 (0x89) */
1146#define RT5645_I2S1_PD_MASK (0x7 << 12)
1147#define RT5645_I2S1_PD_SFT 12
1148#define RT5645_I2S2_PD_MASK (0x7 << 8)
1149#define RT5645_I2S2_PD_SFT 8
1150
1151/* HPOUT Over Current Detection (0x8b) */

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2161 RT5645_DMIC_DATA_GPIO11,
2162};
2163
2164enum {
2165 CODEC_TYPE_RT5645,
2166 CODEC_TYPE_RT5650,
2167};
2168
2169/* filter mask */
2170enum {
2171 RT5645_DA_STEREO_FILTER = 0x1,
2172 RT5645_DA_MONO_L_FILTER = (0x1 << 1),
2173 RT5645_DA_MONO_R_FILTER = (0x1 << 2),
2174 RT5645_AD_STEREO_FILTER = (0x1 << 3),
2175 RT5645_AD_MONO_L_FILTER = (0x1 << 4),
2176 RT5645_AD_MONO_R_FILTER = (0x1 << 5),
2177};
2178
2179int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
2180 unsigned int filter_mask, unsigned int clk_src);
2181
2192struct rt5645_priv {
2193 struct snd_soc_codec *codec;
2194 struct rt5645_platform_data pdata;
2195 struct regmap *regmap;
2196 struct i2c_client *i2c;
2197 struct snd_soc_jack *hp_jack;
2198 struct snd_soc_jack *mic_jack;
2199 struct delayed_work jack_detect_work;

--- 17 unchanged lines hidden --- 		2182struct rt5645_priv {
2183 struct snd_soc_codec *codec;
2184 struct rt5645_platform_data pdata;
2185 struct regmap *regmap;
2186 struct i2c_client *i2c;
2187 struct snd_soc_jack *hp_jack;
2188 struct snd_soc_jack *mic_jack;
2189 struct delayed_work jack_detect_work;

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