| rt5645.h (33de3d54b8b6fc53b9bace4772a70915ca96ecea) | rt5645.h (de97c15b3c74ebc33f5470efaa22112444b80298) |
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| 1/* 2 * rt5645.h -- RT5645 ALSA SoC audio driver 3 * 4 * Copyright 2013 Realtek Microelectronics 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 1049 unchanged lines hidden (view full) --- 1058#define RT5645_IF1_ADC_IN_MASK (0x3 << 8) 1059#define RT5645_IF1_ADC_IN_SFT 8 1060 1061/* Global Clock Control (0x80) */ 1062#define RT5645_SCLK_SRC_MASK (0x3 << 14) 1063#define RT5645_SCLK_SRC_SFT 14 1064#define RT5645_SCLK_SRC_MCLK (0x0 << 14) 1065#define RT5645_SCLK_SRC_PLL1 (0x1 << 14) | 1/* 2 * rt5645.h -- RT5645 ALSA SoC audio driver 3 * 4 * Copyright 2013 Realtek Microelectronics 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 1049 unchanged lines hidden (view full) --- 1058#define RT5645_IF1_ADC_IN_MASK (0x3 << 8) 1059#define RT5645_IF1_ADC_IN_SFT 8 1060 1061/* Global Clock Control (0x80) */ 1062#define RT5645_SCLK_SRC_MASK (0x3 << 14) 1063#define RT5645_SCLK_SRC_SFT 14 1064#define RT5645_SCLK_SRC_MCLK (0x0 << 14) 1065#define RT5645_SCLK_SRC_PLL1 (0x1 << 14) |
| 1066#define RT5645_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */ 1067#define RT5645_PLL1_SRC_MASK (0x3 << 12) 1068#define RT5645_PLL1_SRC_SFT 12 1069#define RT5645_PLL1_SRC_MCLK (0x0 << 12) 1070#define RT5645_PLL1_SRC_BCLK1 (0x1 << 12) 1071#define RT5645_PLL1_SRC_BCLK2 (0x2 << 12) 1072#define RT5645_PLL1_SRC_BCLK3 (0x3 << 12) | 1066#define RT5645_SCLK_SRC_RCCLK (0x2 << 14) 1067#define RT5645_PLL1_SRC_MASK (0x7 << 11) 1068#define RT5645_PLL1_SRC_SFT 11 1069#define RT5645_PLL1_SRC_MCLK (0x0 << 11) 1070#define RT5645_PLL1_SRC_BCLK1 (0x1 << 11) 1071#define RT5645_PLL1_SRC_BCLK2 (0x2 << 11) 1072#define RT5645_PLL1_SRC_BCLK3 (0x3 << 11) 1073#define RT5645_PLL1_SRC_RCCLK (0x4 << 11) |
| 1073#define RT5645_PLL1_PD_MASK (0x1 << 3) 1074#define RT5645_PLL1_PD_SFT 3 1075#define RT5645_PLL1_PD_1 (0x0 << 3) 1076#define RT5645_PLL1_PD_2 (0x1 << 3) 1077 1078#define RT5645_PLL_INP_MAX 40000000 1079#define RT5645_PLL_INP_MIN 256000 1080/* PLL M/N/K Code Control 1 (0x81) */ --- 1124 unchanged lines hidden --- | 1074#define RT5645_PLL1_PD_MASK (0x1 << 3) 1075#define RT5645_PLL1_PD_SFT 3 1076#define RT5645_PLL1_PD_1 (0x0 << 3) 1077#define RT5645_PLL1_PD_2 (0x1 << 3) 1078 1079#define RT5645_PLL_INP_MAX 40000000 1080#define RT5645_PLL_INP_MIN 256000 1081/* PLL M/N/K Code Control 1 (0x81) */ --- 1124 unchanged lines hidden --- |