| rt5645.h (26440c835f8b1a491e2704118ac55bf87334366c) | rt5645.h (bc86e53a0ae9bb26c1af04034e010d8f22b1b0da) |
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| 1/* 2 * rt5645.h -- RT5645 ALSA SoC audio driver 3 * 4 * Copyright 2013 Realtek Microelectronics 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 25 unchanged lines hidden (view full) --- 34#define RT5645_ADJ_HPF_CTRL 0x16 35/* I/O - ADC/DAC/DMIC */ 36#define RT5645_DAC1_DIG_VOL 0x19 37#define RT5645_DAC2_DIG_VOL 0x1a 38#define RT5645_DAC_CTRL 0x1b 39#define RT5645_STO1_ADC_DIG_VOL 0x1c 40#define RT5645_MONO_ADC_DIG_VOL 0x1d 41#define RT5645_ADC_BST_VOL1 0x1e | 1/* 2 * rt5645.h -- RT5645 ALSA SoC audio driver 3 * 4 * Copyright 2013 Realtek Microelectronics 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 25 unchanged lines hidden (view full) --- 34#define RT5645_ADJ_HPF_CTRL 0x16 35/* I/O - ADC/DAC/DMIC */ 36#define RT5645_DAC1_DIG_VOL 0x19 37#define RT5645_DAC2_DIG_VOL 0x1a 38#define RT5645_DAC_CTRL 0x1b 39#define RT5645_STO1_ADC_DIG_VOL 0x1c 40#define RT5645_MONO_ADC_DIG_VOL 0x1d 41#define RT5645_ADC_BST_VOL1 0x1e |
| 42#define RT5645_ADC_BST_VOL2 0x20 | |
| 43/* Mixer - D-D */ | 42/* Mixer - D-D */ |
| 43#define RT5645_ADC_BST_VOL2 0x20 |
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| 44#define RT5645_STO1_ADC_MIXER 0x27 45#define RT5645_MONO_ADC_MIXER 0x28 46#define RT5645_AD_DA_MIXER 0x29 47#define RT5645_STO_DAC_MIXER 0x2a 48#define RT5645_MONO_DAC_MIXER 0x2b 49#define RT5645_DIG_MIXER 0x2c 50#define RT5650_A_DAC_SOUR 0x2d 51#define RT5645_DIG_INF1_DATA 0x2f --- 258 unchanged lines hidden (view full) --- 310 311/* ADC Boost Volume Control (0x1e) */ 312#define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14) 313#define RT5645_STO1_ADC_L_BST_SFT 14 314#define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12) 315#define RT5645_STO1_ADC_R_BST_SFT 12 316#define RT5645_STO1_ADC_COMP_MASK (0x3 << 10) 317#define RT5645_STO1_ADC_COMP_SFT 10 | 44#define RT5645_STO1_ADC_MIXER 0x27 45#define RT5645_MONO_ADC_MIXER 0x28 46#define RT5645_AD_DA_MIXER 0x29 47#define RT5645_STO_DAC_MIXER 0x2a 48#define RT5645_MONO_DAC_MIXER 0x2b 49#define RT5645_DIG_MIXER 0x2c 50#define RT5650_A_DAC_SOUR 0x2d 51#define RT5645_DIG_INF1_DATA 0x2f --- 258 unchanged lines hidden (view full) --- 310 311/* ADC Boost Volume Control (0x1e) */ 312#define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14) 313#define RT5645_STO1_ADC_L_BST_SFT 14 314#define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12) 315#define RT5645_STO1_ADC_R_BST_SFT 12 316#define RT5645_STO1_ADC_COMP_MASK (0x3 << 10) 317#define RT5645_STO1_ADC_COMP_SFT 10 |
| 318#define RT5645_STO2_ADC_L_BST_MASK (0x3 << 8) 319#define RT5645_STO2_ADC_L_BST_SFT 8 320#define RT5645_STO2_ADC_R_BST_MASK (0x3 << 6) 321#define RT5645_STO2_ADC_R_BST_SFT 6 322#define RT5645_STO2_ADC_COMP_MASK (0x3 << 4) 323#define RT5645_STO2_ADC_COMP_SFT 4 |
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| 318 | 324 |
| 319/* ADC Boost Volume Control (0x20) */ 320#define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14) 321#define RT5645_MONO_ADC_L_BST_SFT 14 322#define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12) 323#define RT5645_MONO_ADC_R_BST_SFT 12 324#define RT5645_MONO_ADC_COMP_MASK (0x3 << 10) 325#define RT5645_MONO_ADC_COMP_SFT 10 326 | |
| 327/* Stereo2 ADC Mixer Control (0x26) */ 328#define RT5645_STO2_ADC_SRC_MASK (0x1 << 15) 329#define RT5645_STO2_ADC_SRC_SFT 15 330 331/* Stereo ADC Mixer Control (0x27) */ 332#define RT5645_M_ADC_L1 (0x1 << 14) 333#define RT5645_M_ADC_L1_SFT 14 334#define RT5645_M_ADC_L2 (0x1 << 13) --- 281 unchanged lines hidden (view full) --- 616#define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10) 617#define RT5645_G_DAC_L1_SM_L_SFT 10 618#define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8) 619#define RT5645_G_DAC_L2_SM_L_SFT 8 620#define RT5645_G_OM_L_SM_L_MASK (0x3 << 6) 621#define RT5645_G_OM_L_SM_L_SFT 6 622#define RT5645_M_BST1_L_SM_L (0x1 << 5) 623#define RT5645_M_BST1_L_SM_L_SFT 5 | 325/* Stereo2 ADC Mixer Control (0x26) */ 326#define RT5645_STO2_ADC_SRC_MASK (0x1 << 15) 327#define RT5645_STO2_ADC_SRC_SFT 15 328 329/* Stereo ADC Mixer Control (0x27) */ 330#define RT5645_M_ADC_L1 (0x1 << 14) 331#define RT5645_M_ADC_L1_SFT 14 332#define RT5645_M_ADC_L2 (0x1 << 13) --- 281 unchanged lines hidden (view full) --- 614#define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10) 615#define RT5645_G_DAC_L1_SM_L_SFT 10 616#define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8) 617#define RT5645_G_DAC_L2_SM_L_SFT 8 618#define RT5645_G_OM_L_SM_L_MASK (0x3 << 6) 619#define RT5645_G_OM_L_SM_L_SFT 6 620#define RT5645_M_BST1_L_SM_L (0x1 << 5) 621#define RT5645_M_BST1_L_SM_L_SFT 5 |
| 622#define RT5645_M_BST3_L_SM_L (0x1 << 4) 623#define RT5645_M_BST3_L_SM_L_SFT 4 |
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| 624#define RT5645_M_IN_L_SM_L (0x1 << 3) 625#define RT5645_M_IN_L_SM_L_SFT 3 | 624#define RT5645_M_IN_L_SM_L (0x1 << 3) 625#define RT5645_M_IN_L_SM_L_SFT 3 |
| 626#define RT5645_M_DAC_L1_SM_L (0x1 << 1) 627#define RT5645_M_DAC_L1_SM_L_SFT 1 | |
| 628#define RT5645_M_DAC_L2_SM_L (0x1 << 2) 629#define RT5645_M_DAC_L2_SM_L_SFT 2 | 626#define RT5645_M_DAC_L2_SM_L (0x1 << 2) 627#define RT5645_M_DAC_L2_SM_L_SFT 2 |
| 630#define RT5645_M_BST3_L_SM_L (0x1 << 4) 631#define RT5645_M_BST3_L_SM_L_SFT 4 | 628#define RT5645_M_DAC_L1_SM_L (0x1 << 1) 629#define RT5645_M_DAC_L1_SM_L_SFT 1 |
| 632 633/* SPK Right Mixer Control (0x47) */ 634#define RT5645_G_RM_R_SM_R_MASK (0x3 << 14) 635#define RT5645_G_RM_R_SM_R_SFT 14 636#define RT5645_G_IN_R_SM_R_MASK (0x3 << 12) 637#define RT5645_G_IN_R_SM_R_SFT 12 638#define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10) 639#define RT5645_G_DAC_R1_SM_R_SFT 10 640#define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8) 641#define RT5645_G_DAC_R2_SM_R_SFT 8 642#define RT5645_G_OM_R_SM_R_MASK (0x3 << 6) 643#define RT5645_G_OM_R_SM_R_SFT 6 644#define RT5645_M_BST2_R_SM_R (0x1 << 5) 645#define RT5645_M_BST2_R_SM_R_SFT 5 | 630 631/* SPK Right Mixer Control (0x47) */ 632#define RT5645_G_RM_R_SM_R_MASK (0x3 << 14) 633#define RT5645_G_RM_R_SM_R_SFT 14 634#define RT5645_G_IN_R_SM_R_MASK (0x3 << 12) 635#define RT5645_G_IN_R_SM_R_SFT 12 636#define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10) 637#define RT5645_G_DAC_R1_SM_R_SFT 10 638#define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8) 639#define RT5645_G_DAC_R2_SM_R_SFT 8 640#define RT5645_G_OM_R_SM_R_MASK (0x3 << 6) 641#define RT5645_G_OM_R_SM_R_SFT 6 642#define RT5645_M_BST2_R_SM_R (0x1 << 5) 643#define RT5645_M_BST2_R_SM_R_SFT 5 |
| 644#define RT5645_M_BST3_R_SM_R (0x1 << 4) 645#define RT5645_M_BST3_R_SM_R_SFT 4 |
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| 646#define RT5645_M_IN_R_SM_R (0x1 << 3) 647#define RT5645_M_IN_R_SM_R_SFT 3 | 646#define RT5645_M_IN_R_SM_R (0x1 << 3) 647#define RT5645_M_IN_R_SM_R_SFT 3 |
| 648#define RT5645_M_DAC_R1_SM_R (0x1 << 1) 649#define RT5645_M_DAC_R1_SM_R_SFT 1 | |
| 650#define RT5645_M_DAC_R2_SM_R (0x1 << 2) 651#define RT5645_M_DAC_R2_SM_R_SFT 2 | 648#define RT5645_M_DAC_R2_SM_R (0x1 << 2) 649#define RT5645_M_DAC_R2_SM_R_SFT 2 |
| 652#define RT5645_M_BST3_R_SM_R (0x1 << 4) 653#define RT5645_M_BST3_R_SM_R_SFT 4 | 650#define RT5645_M_DAC_R1_SM_R (0x1 << 1) 651#define RT5645_M_DAC_R1_SM_R_SFT 1 |
| 654 655/* SPOLMIX Control (0x48) */ 656#define RT5645_M_DAC_L1_SPM_L (0x1 << 15) 657#define RT5645_M_DAC_L1_SPM_L_SFT 15 658#define RT5645_M_DAC_R1_SPM_L (0x1 << 14) 659#define RT5645_M_DAC_R1_SPM_L_SFT 14 660#define RT5645_M_SV_L_SPM_L (0x1 << 13) 661#define RT5645_M_SV_L_SPM_L_SFT 13 662#define RT5645_M_SV_R_SPM_L (0x1 << 12) 663#define RT5645_M_SV_R_SPM_L_SFT 12 664#define RT5645_M_BST3_SPM_L (0x1 << 11) 665#define RT5645_M_BST3_SPM_L_SFT 11 666#define RT5645_M_DAC_R1_SPM_R (0x1 << 2) 667#define RT5645_M_DAC_R1_SPM_R_SFT 2 668#define RT5645_M_BST3_SPM_R (0x1 << 1) 669#define RT5645_M_BST3_SPM_R_SFT 1 670#define RT5645_M_SV_R_SPM_R (0x1 << 0) 671#define RT5645_M_SV_R_SPM_R_SFT 0 672 | 652 653/* SPOLMIX Control (0x48) */ 654#define RT5645_M_DAC_L1_SPM_L (0x1 << 15) 655#define RT5645_M_DAC_L1_SPM_L_SFT 15 656#define RT5645_M_DAC_R1_SPM_L (0x1 << 14) 657#define RT5645_M_DAC_R1_SPM_L_SFT 14 658#define RT5645_M_SV_L_SPM_L (0x1 << 13) 659#define RT5645_M_SV_L_SPM_L_SFT 13 660#define RT5645_M_SV_R_SPM_L (0x1 << 12) 661#define RT5645_M_SV_R_SPM_L_SFT 12 662#define RT5645_M_BST3_SPM_L (0x1 << 11) 663#define RT5645_M_BST3_SPM_L_SFT 11 664#define RT5645_M_DAC_R1_SPM_R (0x1 << 2) 665#define RT5645_M_DAC_R1_SPM_R_SFT 2 666#define RT5645_M_BST3_SPM_R (0x1 << 1) 667#define RT5645_M_BST3_SPM_R_SFT 1 668#define RT5645_M_SV_R_SPM_R (0x1 << 0) 669#define RT5645_M_SV_R_SPM_R_SFT 0 670 |
| 671/* SPOMIX Ratio Control (0x4a) */ 672#define RT5645_SPK_G_CLSD_MASK (0x7 << 0) 673#define RT5645_SPK_G_CLSD_SFT 0 674 |
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| 673/* Mono Output Mixer Control (0x4c) */ | 675/* Mono Output Mixer Control (0x4c) */ |
| 676#define RT5645_G_MONOMIX_MASK (0x1 << 10) 677#define RT5645_G_MONOMIX_SFT 10 |
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| 674#define RT5645_M_OV_L_MM (0x1 << 9) 675#define RT5645_M_OV_L_MM_SFT 9 676#define RT5645_M_DAC_L2_MA (0x1 << 8) 677#define RT5645_M_DAC_L2_MA_SFT 8 | 678#define RT5645_M_OV_L_MM (0x1 << 9) 679#define RT5645_M_OV_L_MM_SFT 9 680#define RT5645_M_DAC_L2_MA (0x1 << 8) 681#define RT5645_M_DAC_L2_MA_SFT 8 |
| 678#define RT5645_G_MONOMIX_MASK (0x1 << 10) 679#define RT5645_G_MONOMIX_SFT 10 | |
| 680#define RT5645_M_BST2_MM (0x1 << 4) 681#define RT5645_M_BST2_MM_SFT 4 682#define RT5645_M_DAC_R1_MM (0x1 << 3) 683#define RT5645_M_DAC_R1_MM_SFT 3 684#define RT5645_M_DAC_R2_MM (0x1 << 2) 685#define RT5645_M_DAC_R2_MM_SFT 2 686#define RT5645_M_DAC_L2_MM (0x1 << 1) 687#define RT5645_M_DAC_L2_MM_SFT 1 --- 86 unchanged lines hidden (view full) --- 774#define RT5645_PWR_DAC_L1 (0x1 << 12) 775#define RT5645_PWR_DAC_L1_BIT 12 776#define RT5645_PWR_DAC_R1 (0x1 << 11) 777#define RT5645_PWR_DAC_R1_BIT 11 778#define RT5645_PWR_CLS_D_R (0x1 << 9) 779#define RT5645_PWR_CLS_D_R_BIT 9 780#define RT5645_PWR_CLS_D_L (0x1 << 8) 781#define RT5645_PWR_CLS_D_L_BIT 8 | 682#define RT5645_M_BST2_MM (0x1 << 4) 683#define RT5645_M_BST2_MM_SFT 4 684#define RT5645_M_DAC_R1_MM (0x1 << 3) 685#define RT5645_M_DAC_R1_MM_SFT 3 686#define RT5645_M_DAC_R2_MM (0x1 << 2) 687#define RT5645_M_DAC_R2_MM_SFT 2 688#define RT5645_M_DAC_L2_MM (0x1 << 1) 689#define RT5645_M_DAC_L2_MM_SFT 1 --- 86 unchanged lines hidden (view full) --- 776#define RT5645_PWR_DAC_L1 (0x1 << 12) 777#define RT5645_PWR_DAC_L1_BIT 12 778#define RT5645_PWR_DAC_R1 (0x1 << 11) 779#define RT5645_PWR_DAC_R1_BIT 11 780#define RT5645_PWR_CLS_D_R (0x1 << 9) 781#define RT5645_PWR_CLS_D_R_BIT 9 782#define RT5645_PWR_CLS_D_L (0x1 << 8) 783#define RT5645_PWR_CLS_D_L_BIT 8 |
| 782#define RT5645_PWR_ADC_R (0x1 << 1) 783#define RT5645_PWR_ADC_R_BIT 1 | |
| 784#define RT5645_PWR_DAC_L2 (0x1 << 7) 785#define RT5645_PWR_DAC_L2_BIT 7 786#define RT5645_PWR_DAC_R2 (0x1 << 6) 787#define RT5645_PWR_DAC_R2_BIT 6 788#define RT5645_PWR_ADC_L (0x1 << 2) 789#define RT5645_PWR_ADC_L_BIT 2 790#define RT5645_PWR_ADC_R (0x1 << 1) 791#define RT5645_PWR_ADC_R_BIT 1 --- 831 unchanged lines hidden (view full) --- 1623#define RT5645_JD_P_SFT 11 1624#define RT5645_JD_P_NOR (0x0 << 11) 1625#define RT5645_JD_P_INV (0x1 << 11) 1626#define RT5645_OT_P_MASK (0x1 << 10) 1627#define RT5645_OT_P_SFT 10 1628#define RT5645_OT_P_NOR (0x0 << 10) 1629#define RT5645_OT_P_INV (0x1 << 10) 1630#define RT5645_IRQ_JD_1_1_EN (0x1 << 9) | 784#define RT5645_PWR_DAC_L2 (0x1 << 7) 785#define RT5645_PWR_DAC_L2_BIT 7 786#define RT5645_PWR_DAC_R2 (0x1 << 6) 787#define RT5645_PWR_DAC_R2_BIT 6 788#define RT5645_PWR_ADC_L (0x1 << 2) 789#define RT5645_PWR_ADC_L_BIT 2 790#define RT5645_PWR_ADC_R (0x1 << 1) 791#define RT5645_PWR_ADC_R_BIT 1 --- 831 unchanged lines hidden (view full) --- 1623#define RT5645_JD_P_SFT 11 1624#define RT5645_JD_P_NOR (0x0 << 11) 1625#define RT5645_JD_P_INV (0x1 << 11) 1626#define RT5645_OT_P_MASK (0x1 << 10) 1627#define RT5645_OT_P_SFT 10 1628#define RT5645_OT_P_NOR (0x0 << 10) 1629#define RT5645_OT_P_INV (0x1 << 10) 1630#define RT5645_IRQ_JD_1_1_EN (0x1 << 9) |
| 1631#define RT5645_JD_1_1_MASK (0x1 << 7) 1632#define RT5645_JD_1_1_SFT 7 1633#define RT5645_JD_1_1_NOR (0x0 << 7) 1634#define RT5645_JD_1_1_INV (0x1 << 7) |
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| 1631 1632/* IRQ Control 2 (0xbe) */ 1633#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15) 1634#define RT5645_IRQ_MB1_OC_SFT 15 1635#define RT5645_IRQ_MB1_OC_BP (0x0 << 15) 1636#define RT5645_IRQ_MB1_OC_NOR (0x1 << 15) 1637#define RT5645_IRQ_MB2_OC_MASK (0x1 << 14) 1638#define RT5645_IRQ_MB2_OC_SFT 14 --- 552 unchanged lines hidden --- | 1635 1636/* IRQ Control 2 (0xbe) */ 1637#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15) 1638#define RT5645_IRQ_MB1_OC_SFT 15 1639#define RT5645_IRQ_MB1_OC_BP (0x0 << 15) 1640#define RT5645_IRQ_MB1_OC_NOR (0x1 << 15) 1641#define RT5645_IRQ_MB2_OC_MASK (0x1 << 14) 1642#define RT5645_IRQ_MB2_OC_SFT 14 --- 552 unchanged lines hidden --- |