rt5645.c (786aa09b27be7916c1281d7a29a394bd1ae7a4dc) rt5645.c (ac4fc3eeb79e06499779db99937522526e863ab6)
1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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2963 break;
2964 }
2965
2966 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2967
2968 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
2969
2970 /* for JD function */
1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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2963 break;
2964 }
2965
2966 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2967
2968 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
2969
2970 /* for JD function */
2971 if (rt5645->pdata.en_jd_func) {
2971 if (rt5645->pdata.jd_mode) {
2972 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
2973 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2974 snd_soc_dapm_sync(&codec->dapm);
2975 }
2976
2977 return 0;
2978}
2979

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3106 {},
3107};
3108MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3109#endif
3110
3111static struct rt5645_platform_data *rt5645_pdata;
3112
3113static struct rt5645_platform_data strago_platform_data = {
2972 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
2973 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2974 snd_soc_dapm_sync(&codec->dapm);
2975 }
2976
2977 return 0;
2978}
2979

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3106 {},
3107};
3108MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3109#endif
3110
3111static struct rt5645_platform_data *rt5645_pdata;
3112
3113static struct rt5645_platform_data strago_platform_data = {
3114 .dmic_en = true,
3115 .dmic1_data_pin = -1,
3114 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3116 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3115 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3117 .en_jd_func = true,
3118 .jd_mode = 3,
3119};
3120
3121static int strago_quirk_cb(const struct dmi_system_id *id)
3122{
3123 rt5645_pdata = &strago_platform_data;
3124
3125 return 1;

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3209 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3210 ret);
3211 }
3212
3213 if (rt5645->pdata.in2_diff)
3214 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3215 RT5645_IN_DF2, RT5645_IN_DF2);
3216
3116 .jd_mode = 3,
3117};
3118
3119static int strago_quirk_cb(const struct dmi_system_id *id)
3120{
3121 rt5645_pdata = &strago_platform_data;
3122
3123 return 1;

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3207 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3208 ret);
3209 }
3210
3211 if (rt5645->pdata.in2_diff)
3212 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3213 RT5645_IN_DF2, RT5645_IN_DF2);
3214
3217 if (rt5645->pdata.dmic_en) {
3215 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
3218 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3219 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
3216 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3217 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
3218 }
3219 switch (rt5645->pdata.dmic1_data_pin) {
3220 case RT5645_DMIC_DATA_IN2N:
3221 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3222 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3223 break;
3220
3224
3221 switch (rt5645->pdata.dmic1_data_pin) {
3222 case RT5645_DMIC_DATA_IN2N:
3223 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3224 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3225 break;
3225 case RT5645_DMIC_DATA_GPIO5:
3226 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3227 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3228 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3229 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3230 break;
3226
3231
3227 case RT5645_DMIC_DATA_GPIO5:
3228 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3229 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3230 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3231 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3232 break;
3232 case RT5645_DMIC_DATA_GPIO11:
3233 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3234 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3235 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3236 RT5645_GP11_PIN_MASK,
3237 RT5645_GP11_PIN_DMIC1_SDA);
3238 break;
3233
3239
3234 case RT5645_DMIC_DATA_GPIO11:
3235 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3236 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3237 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3238 RT5645_GP11_PIN_MASK,
3239 RT5645_GP11_PIN_DMIC1_SDA);
3240 break;
3240 default:
3241 break;
3242 }
3241
3243
3242 default:
3243 break;
3244 }
3244 switch (rt5645->pdata.dmic2_data_pin) {
3245 case RT5645_DMIC_DATA_IN2P:
3246 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3247 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3248 break;
3245
3249
3246 switch (rt5645->pdata.dmic2_data_pin) {
3247 case RT5645_DMIC_DATA_IN2P:
3248 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3249 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3250 break;
3250 case RT5645_DMIC_DATA_GPIO6:
3251 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3252 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3253 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3254 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3255 break;
3251
3256
3252 case RT5645_DMIC_DATA_GPIO6:
3253 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3254 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3255 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3256 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3257 break;
3257 case RT5645_DMIC_DATA_GPIO10:
3258 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3259 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3260 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3261 RT5645_GP10_PIN_MASK,
3262 RT5645_GP10_PIN_DMIC2_SDA);
3263 break;
3258
3264
3259 case RT5645_DMIC_DATA_GPIO10:
3260 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3261 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3262 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3263 RT5645_GP10_PIN_MASK,
3264 RT5645_GP10_PIN_DMIC2_SDA);
3265 break;
3265 case RT5645_DMIC_DATA_GPIO12:
3266 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3267 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3268 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3269 RT5645_GP12_PIN_MASK,
3270 RT5645_GP12_PIN_DMIC2_SDA);
3271 break;
3266
3272
3267 case RT5645_DMIC_DATA_GPIO12:
3268 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3269 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3270 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3271 RT5645_GP12_PIN_MASK,
3272 RT5645_GP12_PIN_DMIC2_SDA);
3273 break;
3274
3275 default:
3276 break;
3277 }
3278
3273 default:
3274 break;
3279 }
3280
3275 }
3276
3281 if (rt5645->pdata.en_jd_func) {
3277 if (rt5645->pdata.jd_mode) {
3282 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3278 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3283 RT5645_IRQ_CLK_GATE_CTRL, RT5645_IRQ_CLK_GATE_CTRL);
3279 RT5645_IRQ_CLK_GATE_CTRL,
3280 RT5645_IRQ_CLK_GATE_CTRL);
3284 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3281 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3285 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3282 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3286 regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,
3283 regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,
3287 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,
3288 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);
3284 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,
3285 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);
3289 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3286 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3290 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
3291 }
3292
3293 if (rt5645->pdata.jd_mode) {
3287 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
3294 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3295 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3296 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3297 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3298 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3299 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3300 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3301 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);

--- 79 unchanged lines hidden --- 		3288 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3289 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3290 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3291 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3292 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3293 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3294 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3295 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);

--- 79 unchanged lines hidden ---