cs42l56.c (712cba5d87a6c0e980ee5fad45734e189c4d7151) cs42l56.c (8c317fafdd4e3b988c44d986022c66cebf71fc41)
1/*
2 * cs42l56.c -- CS42L56 ALSA SoC audio driver
3 *
4 * Copyright 2014 CirrusLogic, Inc.
5 *
6 * Author: Brian Austin <brian.austin@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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59#if IS_ENABLED(CONFIG_INPUT)
60 struct input_dev *beep;
61 struct work_struct beep_work;
62 int beep_rate;
63#endif
64};
65
66static const struct reg_default cs42l56_reg_defaults[] = {
1/*
2 * cs42l56.c -- CS42L56 ALSA SoC audio driver
3 *
4 * Copyright 2014 CirrusLogic, Inc.
5 *
6 * Author: Brian Austin <brian.austin@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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59#if IS_ENABLED(CONFIG_INPUT)
60 struct input_dev *beep;
61 struct work_struct beep_work;
62 int beep_rate;
63#endif
64};
65
66static const struct reg_default cs42l56_reg_defaults[] = {
67 { 1, 0x56 }, /* r01 - ID 1 */
68 { 2, 0x04 }, /* r02 - ID 2 */
69 { 3, 0x7f }, /* r03 - Power Ctl 1 */
70 { 4, 0xff }, /* r04 - Power Ctl 2 */
71 { 5, 0x00 }, /* ro5 - Clocking Ctl 1 */
72 { 6, 0x0b }, /* r06 - Clocking Ctl 2 */
73 { 7, 0x00 }, /* r07 - Serial Format */
74 { 8, 0x05 }, /* r08 - Class H Ctl */
75 { 9, 0x0c }, /* r09 - Misc Ctl */
76 { 10, 0x80 }, /* r0a - INT Status */

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1257 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
1258 cs42l56->supplies);
1259 if (ret != 0) {
1260 dev_err(&i2c_client->dev,
1261 "Failed to enable supplies: %d\n", ret);
1262 return ret;
1263 }
1264
67 { 3, 0x7f }, /* r03 - Power Ctl 1 */
68 { 4, 0xff }, /* r04 - Power Ctl 2 */
69 { 5, 0x00 }, /* ro5 - Clocking Ctl 1 */
70 { 6, 0x0b }, /* r06 - Clocking Ctl 2 */
71 { 7, 0x00 }, /* r07 - Serial Format */
72 { 8, 0x05 }, /* r08 - Class H Ctl */
73 { 9, 0x0c }, /* r09 - Misc Ctl */
74 { 10, 0x80 }, /* r0a - INT Status */

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1255 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
1256 cs42l56->supplies);
1257 if (ret != 0) {
1258 dev_err(&i2c_client->dev,
1259 "Failed to enable supplies: %d\n", ret);
1260 return ret;
1261 }
1262
1265 regcache_cache_bypass(cs42l56->regmap, true);
1266
1267 ret = regmap_read(cs42l56->regmap, CS42L56_CHIP_ID_1, &reg);
1268 devid = reg & CS42L56_CHIP_ID_MASK;
1269 if (devid != CS42L56_DEVID) {
1270 dev_err(&i2c_client->dev,
1271 "CS42L56 Device ID (%X). Expected %X\n",
1272 devid, CS42L56_DEVID);
1273 goto err_enable;
1274 }
1275 alpha_rev = reg & CS42L56_AREV_MASK;
1276 metal_rev = reg & CS42L56_MTLREV_MASK;
1277
1278 dev_info(&i2c_client->dev, "Cirrus Logic CS42L56 ");
1279 dev_info(&i2c_client->dev, "Alpha Rev %X Metal Rev %X\n",
1280 alpha_rev, metal_rev);
1281
1263 ret = regmap_read(cs42l56->regmap, CS42L56_CHIP_ID_1, &reg);
1264 devid = reg & CS42L56_CHIP_ID_MASK;
1265 if (devid != CS42L56_DEVID) {
1266 dev_err(&i2c_client->dev,
1267 "CS42L56 Device ID (%X). Expected %X\n",
1268 devid, CS42L56_DEVID);
1269 goto err_enable;
1270 }
1271 alpha_rev = reg & CS42L56_AREV_MASK;
1272 metal_rev = reg & CS42L56_MTLREV_MASK;
1273
1274 dev_info(&i2c_client->dev, "Cirrus Logic CS42L56 ");
1275 dev_info(&i2c_client->dev, "Alpha Rev %X Metal Rev %X\n",
1276 alpha_rev, metal_rev);
1277
1282 regcache_cache_bypass(cs42l56->regmap, false);
1283
1284 if (cs42l56->pdata.ain1a_ref_cfg)
1285 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1278 if (cs42l56->pdata.ain1a_ref_cfg)
1279 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1286 CS42L56_AIN1A_REF_MASK, 1);
1280 CS42L56_AIN1A_REF_MASK,
1281 CS42L56_AIN1A_REF_MASK);
1287
1288 if (cs42l56->pdata.ain1b_ref_cfg)
1289 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1282
1283 if (cs42l56->pdata.ain1b_ref_cfg)
1284 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1290 CS42L56_AIN1B_REF_MASK, 1);
1285 CS42L56_AIN1B_REF_MASK,
1286 CS42L56_AIN1B_REF_MASK);
1291
1292 if (cs42l56->pdata.ain2a_ref_cfg)
1293 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1287
1288 if (cs42l56->pdata.ain2a_ref_cfg)
1289 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1294 CS42L56_AIN2A_REF_MASK, 1);
1290 CS42L56_AIN2A_REF_MASK,
1291 CS42L56_AIN2A_REF_MASK);
1295
1296 if (cs42l56->pdata.ain2b_ref_cfg)
1297 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1292
1293 if (cs42l56->pdata.ain2b_ref_cfg)
1294 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1298 CS42L56_AIN2B_REF_MASK, 1);
1295 CS42L56_AIN2B_REF_MASK,
1296 CS42L56_AIN2B_REF_MASK);
1299
1300 if (cs42l56->pdata.micbias_lvl)
1301 regmap_update_bits(cs42l56->regmap, CS42L56_GAIN_BIAS_CTL,
1302 CS42L56_MIC_BIAS_MASK,
1303 cs42l56->pdata.micbias_lvl);
1304
1305 if (cs42l56->pdata.chgfreq)
1306 regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,

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1298 if (cs42l56->pdata.micbias_lvl)
1299 regmap_update_bits(cs42l56->regmap, CS42L56_GAIN_BIAS_CTL,
1300 CS42L56_MIC_BIAS_MASK,
1301 cs42l56->pdata.micbias_lvl);
1302
1303 if (cs42l56->pdata.chgfreq)
1304 regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,

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