ice1724.c (c93f5a1eca1f6d662d791c14c469b6962e05a08f) ice1724.c (d16be8ed69f3e59d36be8c422508c3a10082fdaa)
1/*
2 * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
3 * VIA VT1720 (Envy24PT)
4 *
5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
6 * 2002 James Stafford <jstafford@ampltd.com>
7 * 2003 Takashi Iwai <tiwai@suse.de>
8 *

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101static int PRO_RATE_LOCKED;
102static int PRO_RATE_RESET = 1;
103static unsigned int PRO_RATE_DEFAULT = 44100;
104
105/*
106 * Basic I/O
107 */
108
1/*
2 * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
3 * VIA VT1720 (Envy24PT)
4 *
5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
6 * 2002 James Stafford <jstafford@ampltd.com>
7 * 2003 Takashi Iwai <tiwai@suse.de>
8 *

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101static int PRO_RATE_LOCKED;
102static int PRO_RATE_RESET = 1;
103static unsigned int PRO_RATE_DEFAULT = 44100;
104
105/*
106 * Basic I/O
107 */
108
109/*
110 * default rates, default clock routines
111 */
112
109/* check whether the clock mode is spdif-in */
113/* check whether the clock mode is spdif-in */
110static inline int is_spdif_master(struct snd_ice1712 *ice)
114static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
111{
112 return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
113}
114
115static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
116{
115{
116 return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
117}
118
119static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
120{
117 return is_spdif_master(ice) || PRO_RATE_LOCKED;
121 return ice->is_spdif_master(ice) || PRO_RATE_LOCKED;
118}
119
120/*
121 * ac97 section
122 */
123
124static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
125{

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386/*
387 */
388
389#define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
390 VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
391#define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
392 VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
393
122}
123
124/*
125 * ac97 section
126 */
127
128static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
129{

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390/*
391 */
392
393#define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
394 VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
395#define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
396 VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
397
394static int get_max_rate(struct snd_ice1712 *ice)
398static const unsigned int stdclock_rate_list[16] = {
399 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
400 22050, 11025, 88200, 176400, 0, 192000, 64000
401};
402
403static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
395{
404{
405 unsigned int rate;
406 rate = stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
407 return rate;
408}
409
410static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
411{
412 int i;
413 for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
414 if (stdclock_rate_list[i] == rate) {
415 outb(i, ICEMT1724(ice, RATE));
416 return;
417 }
418 }
419}
420
421static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
422 unsigned int rate)
423{
424 unsigned char val, old;
425 /* check MT02 */
396 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
426 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
397 if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
398 return 192000;
427 val = old = inb(ICEMT1724(ice, I2S_FORMAT));
428 if (rate > 96000)
429 val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
399 else
430 else
400 return 96000;
401 } else
402 return 48000;
431 val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
432 if (val != old) {
433 outb(val, ICEMT1724(ice, I2S_FORMAT));
434 /* master clock changed */
435 return 1;
436 }
437 }
438 /* no change in master clock */
439 return 0;
403}
404
405static void snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
406 int force)
407{
408 unsigned long flags;
440}
441
442static void snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
443 int force)
444{
445 unsigned long flags;
409 unsigned char val, old;
410 unsigned int i, mclk_change;
446 unsigned char mclk_change;
447 unsigned int i, old_rate;
411
448
412 if (rate > get_max_rate(ice))
449 if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
413 return;
450 return;
414
415 switch (rate) {
416 case 8000: val = 6; break;
417 case 9600: val = 3; break;
418 case 11025: val = 10; break;
419 case 12000: val = 2; break;
420 case 16000: val = 5; break;
421 case 22050: val = 9; break;
422 case 24000: val = 1; break;
423 case 32000: val = 4; break;
424 case 44100: val = 8; break;
425 case 48000: val = 0; break;
426 case 64000: val = 15; break;
427 case 88200: val = 11; break;
428 case 96000: val = 7; break;
429 case 176400: val = 12; break;
430 case 192000: val = 14; break;
431 default:
432 snd_BUG();
433 val = 0;
434 break;
435 }
436
437 spin_lock_irqsave(&ice->reg_lock, flags);
451 spin_lock_irqsave(&ice->reg_lock, flags);
438 if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
452 if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
439 (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
440 /* running? we cannot change the rate now... */
441 spin_unlock_irqrestore(&ice->reg_lock, flags);
442 return;
443 }
444 if (!force && is_pro_rate_locked(ice)) {
445 spin_unlock_irqrestore(&ice->reg_lock, flags);
446 return;
447 }
448
453 (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
454 /* running? we cannot change the rate now... */
455 spin_unlock_irqrestore(&ice->reg_lock, flags);
456 return;
457 }
458 if (!force && is_pro_rate_locked(ice)) {
459 spin_unlock_irqrestore(&ice->reg_lock, flags);
460 return;
461 }
462
449 old = inb(ICEMT1724(ice, RATE));
450 if (force || old != val)
451 outb(val, ICEMT1724(ice, RATE));
463 old_rate = ice->get_rate(ice);
464 if (force || (old_rate != rate))
465 ice->set_rate(ice, rate);
452 else if (rate == ice->cur_rate) {
453 spin_unlock_irqrestore(&ice->reg_lock, flags);
454 return;
455 }
456
457 ice->cur_rate = rate;
458
466 else if (rate == ice->cur_rate) {
467 spin_unlock_irqrestore(&ice->reg_lock, flags);
468 return;
469 }
470
471 ice->cur_rate = rate;
472
459 /* check MT02 */
460 mclk_change = 0;
461 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
462 val = old = inb(ICEMT1724(ice, I2S_FORMAT));
463 if (rate > 96000)
464 val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
465 else
466 val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
467 if (val != old) {
468 outb(val, ICEMT1724(ice, I2S_FORMAT));
469 mclk_change = 1;
470 }
471 }
473 /* setting master clock */
474 mclk_change = ice->set_mclk(ice, rate);
475
472 spin_unlock_irqrestore(&ice->reg_lock, flags);
473
474 if (mclk_change && ice->gpio.i2s_mclk_changed)
475 ice->gpio.i2s_mclk_changed(ice);
476 if (ice->gpio.set_pro_rate)
477 ice->gpio.set_pro_rate(ice, rate);
478
479 /* set up codecs */

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722 .period_bytes_max = (1UL << 18),
723 .periods_min = 2,
724 .periods_max = 1024,
725};
726
727/*
728 * set rate constraints
729 */
476 spin_unlock_irqrestore(&ice->reg_lock, flags);
477
478 if (mclk_change && ice->gpio.i2s_mclk_changed)
479 ice->gpio.i2s_mclk_changed(ice);
480 if (ice->gpio.set_pro_rate)
481 ice->gpio.set_pro_rate(ice, rate);
482
483 /* set up codecs */

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726 .period_bytes_max = (1UL << 18),
727 .periods_min = 2,
728 .periods_max = 1024,
729};
730
731/*
732 * set rate constraints
733 */
730static int set_rate_constraints(struct snd_ice1712 *ice,
731 struct snd_pcm_substream *substream)
734static void set_std_hw_rates(struct snd_ice1712 *ice)
732{
735{
733 struct snd_pcm_runtime *runtime = substream->runtime;
734 if (ice->hw_rates) {
735 /* hardware specific */
736 runtime->hw.rate_min = ice->hw_rates->list[0];
737 runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
738 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
739 return snd_pcm_hw_constraint_list(runtime, 0,
740 SNDRV_PCM_HW_PARAM_RATE,
741 ice->hw_rates);
742 }
743 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
744 /* I2S */
745 /* VT1720 doesn't support more than 96kHz */
746 if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
736 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
737 /* I2S */
738 /* VT1720 doesn't support more than 96kHz */
739 if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
747 return snd_pcm_hw_constraint_list(runtime, 0,
748 SNDRV_PCM_HW_PARAM_RATE,
749 &hw_constraints_rates_192);
750 else {
751 runtime->hw.rates = SNDRV_PCM_RATE_KNOT |
752 SNDRV_PCM_RATE_8000_96000;
753 runtime->hw.rate_max = 96000;
754 return snd_pcm_hw_constraint_list(runtime, 0,
755 SNDRV_PCM_HW_PARAM_RATE,
756 &hw_constraints_rates_96);
757 }
758 } else if (ice->ac97) {
740 ice->hw_rates = &hw_constraints_rates_192;
741 else
742 ice->hw_rates = &hw_constraints_rates_96;
743 } else {
759 /* ACLINK */
744 /* ACLINK */
760 runtime->hw.rate_max = 48000;
761 runtime->hw.rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000;
762 return snd_pcm_hw_constraint_list(runtime, 0,
763 SNDRV_PCM_HW_PARAM_RATE,
764 &hw_constraints_rates_48);
745 ice->hw_rates = &hw_constraints_rates_48;
765 }
746 }
766 return 0;
767}
768
747}
748
749static int set_rate_constraints(struct snd_ice1712 *ice,
750 struct snd_pcm_substream *substream)
751{
752 struct snd_pcm_runtime *runtime = substream->runtime;
753
754 runtime->hw.rate_min = ice->hw_rates->list[0];
755 runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
756 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
757 return snd_pcm_hw_constraint_list(runtime, 0,
758 SNDRV_PCM_HW_PARAM_RATE,
759 ice->hw_rates);
760}
761
769/* multi-channel playback needs alignment 8x32bit regardless of the channels
770 * actually used
771 */
772#define VT1724_BUFFER_ALIGN 0x20
773
774static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
775{
776 struct snd_pcm_runtime *runtime = substream->runtime;

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819 return 0;
820}
821
822static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
823{
824 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
825
826 if (PRO_RATE_RESET)
762/* multi-channel playback needs alignment 8x32bit regardless of the channels
763 * actually used
764 */
765#define VT1724_BUFFER_ALIGN 0x20
766
767static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
768{
769 struct snd_pcm_runtime *runtime = substream->runtime;

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812 return 0;
813}
814
815static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
816{
817 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
818
819 if (PRO_RATE_RESET)
827 snd_vt1724_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
820 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
828 ice->playback_pro_substream = NULL;
829
830 return 0;
831}
832
833static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
834{
835 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
836
837 if (PRO_RATE_RESET)
821 ice->playback_pro_substream = NULL;
822
823 return 0;
824}
825
826static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
827{
828 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
829
830 if (PRO_RATE_RESET)
838 snd_vt1724_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
831 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
839 ice->capture_pro_substream = NULL;
840 return 0;
841}
842
843static struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
844 .open = snd_vt1724_playback_pro_open,
845 .close = snd_vt1724_playback_pro_close,
846 .ioctl = snd_pcm_lib_ioctl,

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975 return 0;
976}
977
978static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
979{
980 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
981
982 if (PRO_RATE_RESET)
832 ice->capture_pro_substream = NULL;
833 return 0;
834}
835
836static struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
837 .open = snd_vt1724_playback_pro_open,
838 .close = snd_vt1724_playback_pro_close,
839 .ioctl = snd_pcm_lib_ioctl,

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968 return 0;
969}
970
971static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
972{
973 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
974
975 if (PRO_RATE_RESET)
983 snd_vt1724_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
976 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
984 ice->playback_con_substream = NULL;
985 if (ice->spdif.ops.close)
986 ice->spdif.ops.close(ice, substream);
987
988 return 0;
989}
990
991static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)

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1011 return 0;
1012}
1013
1014static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
1015{
1016 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1017
1018 if (PRO_RATE_RESET)
977 ice->playback_con_substream = NULL;
978 if (ice->spdif.ops.close)
979 ice->spdif.ops.close(ice, substream);
980
981 return 0;
982}
983
984static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)

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1004 return 0;
1005}
1006
1007static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
1008{
1009 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1010
1011 if (PRO_RATE_RESET)
1019 snd_vt1724_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
1012 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1020 ice->capture_con_substream = NULL;
1021 if (ice->spdif.ops.close)
1022 ice->spdif.ops.close(ice, substream);
1023
1024 return 0;
1025}
1026
1027static struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {

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1157 return 0;
1158}
1159
1160static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
1161{
1162 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1163
1164 if (PRO_RATE_RESET)
1013 ice->capture_con_substream = NULL;
1014 if (ice->spdif.ops.close)
1015 ice->spdif.ops.close(ice, substream);
1016
1017 return 0;
1018}
1019
1020static struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {

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1150 return 0;
1151}
1152
1153static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
1154{
1155 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1156
1157 if (PRO_RATE_RESET)
1165 snd_vt1724_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
1158 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1166 ice->playback_con_substream_ds[substream->number] = NULL;
1167 ice->pcm_reserved[substream->number] = NULL;
1168
1169 return 0;
1170}
1171
1172static struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
1173 .open = snd_vt1724_playback_indep_open,

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1575#endif /* NOT USED YET */
1576
1577/*
1578 * rate
1579 */
1580static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1581 struct snd_ctl_elem_info *uinfo)
1582{
1159 ice->playback_con_substream_ds[substream->number] = NULL;
1160 ice->pcm_reserved[substream->number] = NULL;
1161
1162 return 0;
1163}
1164
1165static struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
1166 .open = snd_vt1724_playback_indep_open,

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1568#endif /* NOT USED YET */
1569
1570/*
1571 * rate
1572 */
1573static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1574 struct snd_ctl_elem_info *uinfo)
1575{
1583 static const char * const texts_1724[] = {
1584 "8000", /* 0: 6 */
1585 "9600", /* 1: 3 */
1586 "11025", /* 2: 10 */
1587 "12000", /* 3: 2 */
1588 "16000", /* 4: 5 */
1589 "22050", /* 5: 9 */
1590 "24000", /* 6: 1 */
1591 "32000", /* 7: 4 */
1592 "44100", /* 8: 8 */
1593 "48000", /* 9: 0 */
1594 "64000", /* 10: 15 */
1595 "88200", /* 11: 11 */
1596 "96000", /* 12: 7 */
1597 "176400", /* 13: 12 */
1598 "192000", /* 14: 14 */
1599 "IEC958 Input", /* 15: -- */
1600 };
1601 static const char * const texts_1720[] = {
1602 "8000", /* 0: 6 */
1603 "9600", /* 1: 3 */
1604 "11025", /* 2: 10 */
1605 "12000", /* 3: 2 */
1606 "16000", /* 4: 5 */
1607 "22050", /* 5: 9 */
1608 "24000", /* 6: 1 */
1609 "32000", /* 7: 4 */
1610 "44100", /* 8: 8 */
1611 "48000", /* 9: 0 */
1612 "64000", /* 10: 15 */
1613 "88200", /* 11: 11 */
1614 "96000", /* 12: 7 */
1615 "IEC958 Input", /* 13: -- */
1616 };
1617 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1618
1619 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1620 uinfo->count = 1;
1576 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1577
1578 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1579 uinfo->count = 1;
1621 uinfo->value.enumerated.items = ice->vt1720 ? 14 : 16;
1580 uinfo->value.enumerated.items = ice->hw_rates->count + 1;
1622 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1623 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1581 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1582 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1624 strcpy(uinfo->value.enumerated.name,
1625 ice->vt1720 ? texts_1720[uinfo->value.enumerated.item] :
1626 texts_1724[uinfo->value.enumerated.item]);
1583 if (uinfo->value.enumerated.item == uinfo->value.enumerated.items - 1)
1584 strcpy(uinfo->value.enumerated.name, "IEC958 Input");
1585 else
1586 sprintf(uinfo->value.enumerated.name, "%d",
1587 ice->hw_rates->list[uinfo->value.enumerated.item]);
1627 return 0;
1628}
1629
1630static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1631 struct snd_ctl_elem_value *ucontrol)
1632{
1633 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1588 return 0;
1589}
1590
1591static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1592 struct snd_ctl_elem_value *ucontrol)
1593{
1594 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1634 static const unsigned char xlate[16] = {
1635 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 13, 255, 14, 10
1636 };
1637 unsigned char val;
1595 unsigned int i, rate;
1638
1639 spin_lock_irq(&ice->reg_lock);
1596
1597 spin_lock_irq(&ice->reg_lock);
1640 if (is_spdif_master(ice)) {
1641 ucontrol->value.enumerated.item[0] = ice->vt1720 ? 13 : 15;
1598 if (ice->is_spdif_master(ice)) {
1599 ucontrol->value.enumerated.item[0] = ice->hw_rates->count;
1642 } else {
1600 } else {
1643 val = xlate[inb(ICEMT1724(ice, RATE)) & 15];
1644 if (val == 255) {
1645 snd_BUG();
1646 val = 0;
1601 rate = ice->get_rate(ice);
1602 ucontrol->value.enumerated.item[0] = 0;
1603 for (i = 0; i < ice->hw_rates->count; i++) {
1604 if (ice->hw_rates->list[i] == rate) {
1605 ucontrol->value.enumerated.item[0] = i;
1606 break;
1607 }
1647 }
1608 }
1648 ucontrol->value.enumerated.item[0] = val;
1649 }
1650 spin_unlock_irq(&ice->reg_lock);
1651 return 0;
1652}
1653
1609 }
1610 spin_unlock_irq(&ice->reg_lock);
1611 return 0;
1612}
1613
1614/* setting clock to external - SPDIF */
1615static void stdclock_set_spdif_clock(struct snd_ice1712 *ice)
1616{
1617 unsigned char oval;
1618 unsigned char i2s_oval;
1619 oval = inb(ICEMT1724(ice, RATE));
1620 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1621 /* setting 256fs */
1622 i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
1623 outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
1624}
1625
1654static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1655 struct snd_ctl_elem_value *ucontrol)
1656{
1657 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1626static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1627 struct snd_ctl_elem_value *ucontrol)
1628{
1629 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1658 unsigned char oval;
1659 int rate;
1660 int change = 0;
1661 int spdif = ice->vt1720 ? 13 : 15;
1630 unsigned int old_rate, new_rate;
1631 unsigned int item = ucontrol->value.enumerated.item[0];
1632 unsigned int spdif = ice->hw_rates->count;
1662
1633
1634 if (item > spdif)
1635 return -EINVAL;
1636
1663 spin_lock_irq(&ice->reg_lock);
1637 spin_lock_irq(&ice->reg_lock);
1664 oval = inb(ICEMT1724(ice, RATE));
1665 if (ucontrol->value.enumerated.item[0] == spdif) {
1666 unsigned char i2s_oval;
1667 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1668 /* setting 256fs */
1669 i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
1670 outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X,
1671 ICEMT1724(ice, I2S_FORMAT));
1638 if (ice->is_spdif_master(ice))
1639 old_rate = 0;
1640 else
1641 old_rate = ice->get_rate(ice);
1642 if (item == spdif) {
1643 /* switching to external clock via SPDIF */
1644 ice->set_spdif_clock(ice);
1645 new_rate = 0;
1672 } else {
1646 } else {
1673 rate = rates[ucontrol->value.integer.value[0] % 15];
1674 if (rate <= get_max_rate(ice)) {
1675 PRO_RATE_DEFAULT = rate;
1676 spin_unlock_irq(&ice->reg_lock);
1677 snd_vt1724_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
1678 spin_lock_irq(&ice->reg_lock);
1679 }
1647 /* internal on-card clock */
1648 new_rate = ice->hw_rates->list[item];
1649 ice->pro_rate_default = new_rate;
1650 spin_unlock_irq(&ice->reg_lock);
1651 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
1652 spin_lock_irq(&ice->reg_lock);
1680 }
1653 }
1681 change = inb(ICEMT1724(ice, RATE)) != oval;
1682 spin_unlock_irq(&ice->reg_lock);
1683
1654 spin_unlock_irq(&ice->reg_lock);
1655
1684 if ((oval & VT1724_SPDIF_MASTER) !=
1685 (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER)) {
1656 /* the first reset to the SPDIF master mode? */
1657 if (old_rate != new_rate && !new_rate) {
1686 /* notify akm chips as well */
1658 /* notify akm chips as well */
1687 if (is_spdif_master(ice)) {
1688 unsigned int i;
1689 for (i = 0; i < ice->akm_codecs; i++) {
1690 if (ice->akm[i].ops.set_rate_val)
1691 ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
1692 }
1659 unsigned int i;
1660 if (ice->gpio.set_pro_rate)
1661 ice->gpio.set_pro_rate(ice, 0);
1662 for (i = 0; i < ice->akm_codecs; i++) {
1663 if (ice->akm[i].ops.set_rate_val)
1664 ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
1693 }
1694 }
1665 }
1666 }
1695 return change;
1667 return old_rate != new_rate;
1696}
1697
1698static struct snd_kcontrol_new snd_vt1724_pro_internal_clock __devinitdata = {
1699 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1700 .name = "Multi Track Internal Clock",
1701 .info = snd_vt1724_pro_internal_clock_info,
1702 .get = snd_vt1724_pro_internal_clock_get,
1703 .put = snd_vt1724_pro_internal_clock_put

--- 634 unchanged lines hidden (view full) ---

2338 /*
2339 * VT1724 has separate DMAs for the analog and the SPDIF streams while
2340 * ICE1712 has only one for both (mixed up).
2341 *
2342 * Confusingly the analog PCM is named "professional" here because it
2343 * was called so in ice1712 driver, and vt1724 driver is derived from
2344 * ice1712 driver.
2345 */
1668}
1669
1670static struct snd_kcontrol_new snd_vt1724_pro_internal_clock __devinitdata = {
1671 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1672 .name = "Multi Track Internal Clock",
1673 .info = snd_vt1724_pro_internal_clock_info,
1674 .get = snd_vt1724_pro_internal_clock_get,
1675 .put = snd_vt1724_pro_internal_clock_put

--- 634 unchanged lines hidden (view full) ---

2310 /*
2311 * VT1724 has separate DMAs for the analog and the SPDIF streams while
2312 * ICE1712 has only one for both (mixed up).
2313 *
2314 * Confusingly the analog PCM is named "professional" here because it
2315 * was called so in ice1712 driver, and vt1724 driver is derived from
2316 * ice1712 driver.
2317 */
2318 ice->pro_rate_default = PRO_RATE_DEFAULT;
2319 if (!ice->is_spdif_master)
2320 ice->is_spdif_master = stdclock_is_spdif_master;
2321 if (!ice->get_rate)
2322 ice->get_rate = stdclock_get_rate;
2323 if (!ice->set_rate)
2324 ice->set_rate = stdclock_set_rate;
2325 if (!ice->set_mclk)
2326 ice->set_mclk = stdclock_set_mclk;
2327 if (!ice->set_spdif_clock)
2328 ice->set_spdif_clock = stdclock_set_spdif_clock;
2329 if (!ice->hw_rates)
2330 set_std_hw_rates(ice);
2346
2347 if ((err = snd_vt1724_pcm_profi(ice, pcm_dev++)) < 0) {
2348 snd_card_free(card);
2349 return err;
2350 }
2351
2352 if ((err = snd_vt1724_pcm_spdif(ice, pcm_dev++)) < 0) {
2353 snd_card_free(card);

--- 82 unchanged lines hidden --- 		2331
2332 if ((err = snd_vt1724_pcm_profi(ice, pcm_dev++)) < 0) {
2333 snd_card_free(card);
2334 return err;
2335 }
2336
2337 if ((err = snd_vt1724_pcm_spdif(ice, pcm_dev++)) < 0) {
2338 snd_card_free(card);

--- 82 unchanged lines hidden ---