io.c (11ee59bdac36ae4b500301a6a3ccf586d3968d92) | io.c (6ab13291ba82e6f0c8778cb45726dffffb9205f5) |
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1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for control of EMU10K1 chips 6 * 7 * BUGS: 8 * -- --- 284 unchanged lines hidden (view full) --- 293{ 294 unsigned long flags; 295 296 spin_lock_irqsave(&emu->emu_lock, flags); 297 snd_emu1010_fpga_write_locked(emu, reg, value); 298 spin_unlock_irqrestore(&emu->emu_lock, flags); 299} 300 | 1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for control of EMU10K1 chips 6 * 7 * BUGS: 8 * -- --- 284 unchanged lines hidden (view full) --- 293{ 294 unsigned long flags; 295 296 spin_lock_irqsave(&emu->emu_lock, flags); 297 snd_emu1010_fpga_write_locked(emu, reg, value); 298 spin_unlock_irqrestore(&emu->emu_lock, flags); 299} 300 |
301void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value) | 301static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value) |
302{ 303 // The higest input pin is used as the designated interrupt trigger, 304 // so it needs to be masked out. 305 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f; | 302{ 303 // The higest input pin is used as the designated interrupt trigger, 304 // so it needs to be masked out. 305 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f; |
306 unsigned long flags; | |
307 if (snd_BUG_ON(reg > 0x3f)) 308 return; 309 reg += 0x40; /* 0x40 upwards are registers. */ | 306 if (snd_BUG_ON(reg > 0x3f)) 307 return; 308 reg += 0x40; /* 0x40 upwards are registers. */ |
310 spin_lock_irqsave(&emu->emu_lock, flags); | |
311 outw(reg, emu->port + A_GPIO); 312 udelay(10); 313 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 314 udelay(10); 315 *value = ((inw(emu->port + A_GPIO) >> 8) & mask); | 309 outw(reg, emu->port + A_GPIO); 310 udelay(10); 311 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 312 udelay(10); 313 *value = ((inw(emu->port + A_GPIO) >> 8) & mask); |
314} 315 316void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value) 317{ 318 unsigned long flags; 319 320 spin_lock_irqsave(&emu->emu_lock, flags); 321 snd_emu1010_fpga_read_locked(emu, reg, value); |
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316 spin_unlock_irqrestore(&emu->emu_lock, flags); 317} 318 319/* Each Destination has one and only one Source, 320 * but one Source can feed any number of Destinations simultaneously. 321 */ 322void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src) 323{ --- 6 unchanged lines hidden (view full) --- 330 spin_lock_irqsave(&emu->emu_lock, flags); 331 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 332 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 333 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8); 334 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f); 335 spin_unlock_irqrestore(&emu->emu_lock, flags); 336} 337 | 322 spin_unlock_irqrestore(&emu->emu_lock, flags); 323} 324 325/* Each Destination has one and only one Source, 326 * but one Source can feed any number of Destinations simultaneously. 327 */ 328void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src) 329{ --- 6 unchanged lines hidden (view full) --- 336 spin_lock_irqsave(&emu->emu_lock, flags); 337 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 338 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 339 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8); 340 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f); 341 spin_unlock_irqrestore(&emu->emu_lock, flags); 342} 343 |
344u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst) 345{ 346 unsigned long flags; 347 u32 hi, lo; 348 349 if (snd_BUG_ON(dst & ~0x71f)) 350 return 0; 351 spin_lock_irqsave(&emu->emu_lock, flags); 352 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 353 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 354 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi); 355 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo); 356 spin_unlock_irqrestore(&emu->emu_lock, flags); 357 return (hi << 8) | lo; 358} 359 |
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338void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb) 339{ 340 unsigned long flags; 341 unsigned int enable; 342 343 spin_lock_irqsave(&emu->emu_lock, flags); 344 enable = inl(emu->port + INTE) | intrenb; 345 outl(enable, emu->port + INTE); --- 286 unchanged lines hidden --- | 360void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb) 361{ 362 unsigned long flags; 363 unsigned int enable; 364 365 spin_lock_irqsave(&emu->emu_lock, flags); 366 enable = inl(emu->port + INTE) | intrenb; 367 outl(enable, emu->port + INTE); --- 286 unchanged lines hidden --- |