mlx5-abi.h (664b0bae0b87f69bc9deb098f5e0158b9cf18e04) mlx5-abi.h (24da00164f7a9c247d2224a54494d0e955199630)
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the

--- 70 unchanged lines hidden (view full) ---

79 __u32 total_num_bfregs;
80 __u32 num_low_latency_bfregs;
81 __u32 flags;
82 __u32 comp_mask;
83 __u8 max_cqe_version;
84 __u8 reserved0;
85 __u16 reserved1;
86 __u32 reserved2;
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the

--- 70 unchanged lines hidden (view full) ---

79 __u32 total_num_bfregs;
80 __u32 num_low_latency_bfregs;
81 __u32 flags;
82 __u32 comp_mask;
83 __u8 max_cqe_version;
84 __u8 reserved0;
85 __u16 reserved1;
86 __u32 reserved2;
87 __u64 lib_caps;
87 __aligned_u64 lib_caps;
88};
89
90enum mlx5_ib_alloc_ucontext_resp_mask {
91 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
92};
93
94enum mlx5_user_cmds_supp_uhw {
95 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,

--- 6 unchanged lines hidden (view full) ---

102enum mlx5_user_inline_mode {
103 MLX5_USER_INLINE_MODE_NA,
104 MLX5_USER_INLINE_MODE_NONE,
105 MLX5_USER_INLINE_MODE_L2,
106 MLX5_USER_INLINE_MODE_IP,
107 MLX5_USER_INLINE_MODE_TCP_UDP,
108};
109
88};
89
90enum mlx5_ib_alloc_ucontext_resp_mask {
91 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
92};
93
94enum mlx5_user_cmds_supp_uhw {
95 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,

--- 6 unchanged lines hidden (view full) ---

102enum mlx5_user_inline_mode {
103 MLX5_USER_INLINE_MODE_NA,
104 MLX5_USER_INLINE_MODE_NONE,
105 MLX5_USER_INLINE_MODE_L2,
106 MLX5_USER_INLINE_MODE_IP,
107 MLX5_USER_INLINE_MODE_TCP_UDP,
108};
109
110enum {
111 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
112 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
113 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
114 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
115 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
116};
117
110struct mlx5_ib_alloc_ucontext_resp {
111 __u32 qp_tab_size;
112 __u32 bf_reg_size;
113 __u32 tot_bfregs;
114 __u32 cache_line_size;
115 __u16 max_sq_desc_sz;
116 __u16 max_rq_desc_sz;
117 __u32 max_send_wqebb;
118 __u32 max_recv_wr;
119 __u32 max_srq_recv_wr;
120 __u16 num_ports;
118struct mlx5_ib_alloc_ucontext_resp {
119 __u32 qp_tab_size;
120 __u32 bf_reg_size;
121 __u32 tot_bfregs;
122 __u32 cache_line_size;
123 __u16 max_sq_desc_sz;
124 __u16 max_rq_desc_sz;
125 __u32 max_send_wqebb;
126 __u32 max_recv_wr;
127 __u32 max_srq_recv_wr;
128 __u16 num_ports;
121 __u16 reserved1;
129 __u16 flow_action_flags;
122 __u32 comp_mask;
123 __u32 response_length;
124 __u8 cqe_version;
125 __u8 cmds_supp_uhw;
126 __u8 eth_min_inline;
127 __u8 clock_info_versions;
130 __u32 comp_mask;
131 __u32 response_length;
132 __u8 cqe_version;
133 __u8 cmds_supp_uhw;
134 __u8 eth_min_inline;
135 __u8 clock_info_versions;
128 __u64 hca_core_clock_offset;
136 __aligned_u64 hca_core_clock_offset;
129 __u32 log_uar_size;
130 __u32 num_uars_per_page;
131 __u32 num_dyn_bfregs;
132 __u32 reserved3;
133};
134
135struct mlx5_ib_alloc_pd_resp {
136 __u32 pdn;

--- 5 unchanged lines hidden (view full) ---

142 /* Corresponding bit will be set if qp type from
143 * 'enum ib_qp_type' is supported, e.g.
144 * supported_qpts |= 1 << IB_QPT_UD
145 */
146 __u32 supported_qpts;
147};
148
149struct mlx5_ib_rss_caps {
137 __u32 log_uar_size;
138 __u32 num_uars_per_page;
139 __u32 num_dyn_bfregs;
140 __u32 reserved3;
141};
142
143struct mlx5_ib_alloc_pd_resp {
144 __u32 pdn;

--- 5 unchanged lines hidden (view full) ---

150 /* Corresponding bit will be set if qp type from
151 * 'enum ib_qp_type' is supported, e.g.
152 * supported_qpts |= 1 << IB_QPT_UD
153 */
154 __u32 supported_qpts;
155};
156
157struct mlx5_ib_rss_caps {
150 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
158 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
151 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
152 __u8 reserved[7];
153};
154
155enum mlx5_ib_cqe_comp_res_format {
156 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
157 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
158 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
159};
160
161struct mlx5_ib_cqe_comp_caps {
162 __u32 max_num;
163 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
164};
165
159 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
160 __u8 reserved[7];
161};
162
163enum mlx5_ib_cqe_comp_res_format {
164 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
165 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
166 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
167};
168
169struct mlx5_ib_cqe_comp_caps {
170 __u32 max_num;
171 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
172};
173
174enum mlx5_ib_packet_pacing_cap_flags {
175 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
176};
177
166struct mlx5_packet_pacing_caps {
167 __u32 qp_rate_limit_min;
168 __u32 qp_rate_limit_max; /* In kpbs */
169
170 /* Corresponding bit will be set if qp type from
171 * 'enum ib_qp_type' is supported, e.g.
172 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
173 */
174 __u32 supported_qpts;
178struct mlx5_packet_pacing_caps {
179 __u32 qp_rate_limit_min;
180 __u32 qp_rate_limit_max; /* In kpbs */
181
182 /* Corresponding bit will be set if qp type from
183 * 'enum ib_qp_type' is supported, e.g.
184 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
185 */
186 __u32 supported_qpts;
175 __u32 reserved;
187 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
188 __u8 reserved[3];
176};
177
178enum mlx5_ib_mpw_caps {
179 MPW_RESERVED = 1 << 0,
180 MLX5_IB_ALLOW_MPW = 1 << 1,
181 MLX5_IB_SUPPORT_EMPW = 1 << 2,
182};
183

--- 54 unchanged lines hidden (view full) ---

238 __u32 reserved;
239};
240
241enum mlx5_ib_create_cq_flags {
242 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
243};
244
245struct mlx5_ib_create_cq {
189};
190
191enum mlx5_ib_mpw_caps {
192 MPW_RESERVED = 1 << 0,
193 MLX5_IB_ALLOW_MPW = 1 << 1,
194 MLX5_IB_SUPPORT_EMPW = 1 << 2,
195};
196

--- 54 unchanged lines hidden (view full) ---

251 __u32 reserved;
252};
253
254enum mlx5_ib_create_cq_flags {
255 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
256};
257
258struct mlx5_ib_create_cq {
246 __u64 buf_addr;
247 __u64 db_addr;
259 __aligned_u64 buf_addr;
260 __aligned_u64 db_addr;
248 __u32 cqe_size;
249 __u8 cqe_comp_en;
250 __u8 cqe_comp_res_format;
251 __u16 flags;
252};
253
254struct mlx5_ib_create_cq_resp {
255 __u32 cqn;
256 __u32 reserved;
257};
258
259struct mlx5_ib_resize_cq {
261 __u32 cqe_size;
262 __u8 cqe_comp_en;
263 __u8 cqe_comp_res_format;
264 __u16 flags;
265};
266
267struct mlx5_ib_create_cq_resp {
268 __u32 cqn;
269 __u32 reserved;
270};
271
272struct mlx5_ib_resize_cq {
260 __u64 buf_addr;
273 __aligned_u64 buf_addr;
261 __u16 cqe_size;
262 __u16 reserved0;
263 __u32 reserved1;
264};
265
266struct mlx5_ib_create_srq {
274 __u16 cqe_size;
275 __u16 reserved0;
276 __u32 reserved1;
277};
278
279struct mlx5_ib_create_srq {
267 __u64 buf_addr;
268 __u64 db_addr;
280 __aligned_u64 buf_addr;
281 __aligned_u64 db_addr;
269 __u32 flags;
270 __u32 reserved0; /* explicit padding (optional on i386) */
271 __u32 uidx;
272 __u32 reserved1;
273};
274
275struct mlx5_ib_create_srq_resp {
276 __u32 srqn;
277 __u32 reserved;
278};
279
280struct mlx5_ib_create_qp {
282 __u32 flags;
283 __u32 reserved0; /* explicit padding (optional on i386) */
284 __u32 uidx;
285 __u32 reserved1;
286};
287
288struct mlx5_ib_create_srq_resp {
289 __u32 srqn;
290 __u32 reserved;
291};
292
293struct mlx5_ib_create_qp {
281 __u64 buf_addr;
282 __u64 db_addr;
294 __aligned_u64 buf_addr;
295 __aligned_u64 db_addr;
283 __u32 sq_wqe_count;
284 __u32 rq_wqe_count;
285 __u32 rq_wqe_shift;
286 __u32 flags;
287 __u32 uidx;
288 __u32 bfreg_index;
289 union {
296 __u32 sq_wqe_count;
297 __u32 rq_wqe_count;
298 __u32 rq_wqe_shift;
299 __u32 flags;
300 __u32 uidx;
301 __u32 bfreg_index;
302 union {
290 __u64 sq_buf_addr;
291 __u64 access_key;
303 __aligned_u64 sq_buf_addr;
304 __aligned_u64 access_key;
292 };
293};
294
295/* RX Hash function flags */
296enum mlx5_rx_hash_function_flags {
297 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
298};
299

--- 9 unchanged lines hidden (view full) ---

309 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
310 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
311 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
312 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
313 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
314 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
315 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
316 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
305 };
306};
307
308/* RX Hash function flags */
309enum mlx5_rx_hash_function_flags {
310 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
311};
312

--- 9 unchanged lines hidden (view full) ---

322 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
323 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
324 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
325 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
326 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
327 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
328 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
329 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
330 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
317 /* Save bits for future fields */
318 MLX5_RX_HASH_INNER = (1UL << 31),
319};
320
321struct mlx5_ib_create_qp_rss {
331 /* Save bits for future fields */
332 MLX5_RX_HASH_INNER = (1UL << 31),
333};
334
335struct mlx5_ib_create_qp_rss {
322 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
336 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
323 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
324 __u8 rx_key_len; /* valid only for Toeplitz */
325 __u8 reserved[6];
326 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
327 __u32 comp_mask;
328 __u32 flags;
329};
330
331struct mlx5_ib_create_qp_resp {
332 __u32 bfreg_index;
337 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
338 __u8 rx_key_len; /* valid only for Toeplitz */
339 __u8 reserved[6];
340 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
341 __u32 comp_mask;
342 __u32 flags;
343};
344
345struct mlx5_ib_create_qp_resp {
346 __u32 bfreg_index;
347 __u32 reserved;
333};
334
335struct mlx5_ib_alloc_mw {
336 __u32 comp_mask;
337 __u8 num_klms;
338 __u8 reserved1;
339 __u16 reserved2;
340};
341
342enum mlx5_ib_create_wq_mask {
343 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
344};
345
346struct mlx5_ib_create_wq {
348};
349
350struct mlx5_ib_alloc_mw {
351 __u32 comp_mask;
352 __u8 num_klms;
353 __u8 reserved1;
354 __u16 reserved2;
355};
356
357enum mlx5_ib_create_wq_mask {
358 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
359};
360
361struct mlx5_ib_create_wq {
347 __u64 buf_addr;
348 __u64 db_addr;
362 __aligned_u64 buf_addr;
363 __aligned_u64 db_addr;
349 __u32 rq_wqe_count;
350 __u32 rq_wqe_shift;
351 __u32 user_index;
352 __u32 flags;
353 __u32 comp_mask;
354 __u32 single_stride_log_num_of_bytes;
355 __u32 single_wqe_log_num_of_strides;
356 __u32 two_byte_shift_en;
357};
358
359struct mlx5_ib_create_ah_resp {
360 __u32 response_length;
361 __u8 dmac[ETH_ALEN];
362 __u8 reserved[6];
363};
364
364 __u32 rq_wqe_count;
365 __u32 rq_wqe_shift;
366 __u32 user_index;
367 __u32 flags;
368 __u32 comp_mask;
369 __u32 single_stride_log_num_of_bytes;
370 __u32 single_wqe_log_num_of_strides;
371 __u32 two_byte_shift_en;
372};
373
374struct mlx5_ib_create_ah_resp {
375 __u32 response_length;
376 __u8 dmac[ETH_ALEN];
377 __u8 reserved[6];
378};
379
380struct mlx5_ib_burst_info {
381 __u32 max_burst_sz;
382 __u16 typical_pkt_sz;
383 __u16 reserved;
384};
385
386struct mlx5_ib_modify_qp {
387 __u32 comp_mask;
388 struct mlx5_ib_burst_info burst_info;
389 __u32 reserved;
390};
391
365struct mlx5_ib_modify_qp_resp {
366 __u32 response_length;
367 __u32 dctn;
368};
369
370struct mlx5_ib_create_wq_resp {
371 __u32 response_length;
372 __u32 reserved;

--- 7 unchanged lines hidden (view full) ---

380struct mlx5_ib_modify_wq {
381 __u32 comp_mask;
382 __u32 reserved;
383};
384
385struct mlx5_ib_clock_info {
386 __u32 sign;
387 __u32 resv;
392struct mlx5_ib_modify_qp_resp {
393 __u32 response_length;
394 __u32 dctn;
395};
396
397struct mlx5_ib_create_wq_resp {
398 __u32 response_length;
399 __u32 reserved;

--- 7 unchanged lines hidden (view full) ---

407struct mlx5_ib_modify_wq {
408 __u32 comp_mask;
409 __u32 reserved;
410};
411
412struct mlx5_ib_clock_info {
413 __u32 sign;
414 __u32 resv;
388 __u64 nsec;
389 __u64 cycles;
390 __u64 frac;
415 __aligned_u64 nsec;
416 __aligned_u64 cycles;
417 __aligned_u64 frac;
391 __u32 mult;
392 __u32 shift;
418 __u32 mult;
419 __u32 shift;
393 __u64 mask;
394 __u64 overflow_period;
420 __aligned_u64 mask;
421 __aligned_u64 overflow_period;
395};
396
397enum mlx5_ib_mmap_cmd {
398 MLX5_IB_MMAP_REGULAR_PAGE = 0,
399 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
400 MLX5_IB_MMAP_WC_PAGE = 2,
401 MLX5_IB_MMAP_NC_PAGE = 3,
402 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
403 MLX5_IB_MMAP_CORE_CLOCK = 5,
404 MLX5_IB_MMAP_ALLOC_WC = 6,
405 MLX5_IB_MMAP_CLOCK_INFO = 7,
422};
423
424enum mlx5_ib_mmap_cmd {
425 MLX5_IB_MMAP_REGULAR_PAGE = 0,
426 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
427 MLX5_IB_MMAP_WC_PAGE = 2,
428 MLX5_IB_MMAP_NC_PAGE = 3,
429 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
430 MLX5_IB_MMAP_CORE_CLOCK = 5,
431 MLX5_IB_MMAP_ALLOC_WC = 6,
432 MLX5_IB_MMAP_CLOCK_INFO = 7,
433 MLX5_IB_MMAP_DEVICE_MEM = 8,
406};
407
408enum {
409 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
410};
411
412/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
413enum {
414 MLX5_IB_CLOCK_INFO_V1 = 0,
415};
416#endif /* MLX5_ABI_USER_H */
434};
435
436enum {
437 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
438};
439
440/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
441enum {
442 MLX5_IB_CLOCK_INFO_V1 = 0,
443};
444#endif /* MLX5_ABI_USER_H */