soc-dai.h (17841020e9d3dbd4e8114c2142c2bc6d45c01da1) soc-dai.h (75d9ac46b99280f5f381927ae75a9eaf21844d20)
1/*
2 * linux/sound/soc-dai.h -- ALSA SoC Layer
3 *
4 * Copyright: 2005-2008 Wolfson Microelectronics. PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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19struct snd_pcm_substream;
20
21/*
22 * DAI hardware audio formats.
23 *
24 * Describes the physical PCM data formating and clocking. Add new formats
25 * to the end.
26 */
1/*
2 * linux/sound/soc-dai.h -- ALSA SoC Layer
3 *
4 * Copyright: 2005-2008 Wolfson Microelectronics. PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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19struct snd_pcm_substream;
20
21/*
22 * DAI hardware audio formats.
23 *
24 * Describes the physical PCM data formating and clocking. Add new formats
25 * to the end.
26 */
27#define SND_SOC_DAIFMT_I2S 0 /* I2S mode */
28#define SND_SOC_DAIFMT_RIGHT_J 1 /* Right Justified mode */
29#define SND_SOC_DAIFMT_LEFT_J 2 /* Left Justified mode */
30#define SND_SOC_DAIFMT_DSP_A 3 /* L data MSB after FRM LRC */
31#define SND_SOC_DAIFMT_DSP_B 4 /* L data MSB during FRM LRC */
32#define SND_SOC_DAIFMT_AC97 5 /* AC97 */
33#define SND_SOC_DAIFMT_PDM 6 /* Pulse density modulation */
27#define SND_SOC_DAIFMT_I2S 1 /* I2S mode */
28#define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */
29#define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */
30#define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */
31#define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */
32#define SND_SOC_DAIFMT_AC97 6 /* AC97 */
33#define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */
34
35/* left and right justified also known as MSB and LSB respectively */
36#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J
37#define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J
38
39/*
40 * DAI Clock gating.
41 *
42 * DAI bit clocks can be be gated (disabled) when the DAI is not
43 * sending or receiving PCM data in a frame. This can be used to save power.
44 */
34
35/* left and right justified also known as MSB and LSB respectively */
36#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J
37#define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J
38
39/*
40 * DAI Clock gating.
41 *
42 * DAI bit clocks can be be gated (disabled) when the DAI is not
43 * sending or receiving PCM data in a frame. This can be used to save power.
44 */
45#define SND_SOC_DAIFMT_CONT (0 << 4) /* continuous clock */
46#define SND_SOC_DAIFMT_GATED (1 << 4) /* clock is gated */
45#define SND_SOC_DAIFMT_CONT (1 << 4) /* continuous clock */
46#define SND_SOC_DAIFMT_GATED (2 << 4) /* clock is gated */
47
48/*
49 * DAI hardware signal inversions.
50 *
51 * Specifies whether the DAI can also support inverted clocks for the specified
52 * format.
53 */
47
48/*
49 * DAI hardware signal inversions.
50 *
51 * Specifies whether the DAI can also support inverted clocks for the specified
52 * format.
53 */
54#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */
55#define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal BCLK + inv FRM */
56#define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert BCLK + nor FRM */
57#define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert BCLK + FRM */
54#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */
55#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
56#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */
57#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */
58
59/*
60 * DAI hardware clock masters.
61 *
62 * This is wrt the codec, the inverse is true for the interface
63 * i.e. if the codec is clk and FRM master then the interface is
64 * clk and frame slave.
65 */
58
59/*
60 * DAI hardware clock masters.
61 *
62 * This is wrt the codec, the inverse is true for the interface
63 * i.e. if the codec is clk and FRM master then the interface is
64 * clk and frame slave.
65 */
66#define SND_SOC_DAIFMT_CBM_CFM (0 << 12) /* codec clk & FRM master */
67#define SND_SOC_DAIFMT_CBS_CFM (1 << 12) /* codec clk slave & FRM master */
68#define SND_SOC_DAIFMT_CBM_CFS (2 << 12) /* codec clk master & frame slave */
69#define SND_SOC_DAIFMT_CBS_CFS (3 << 12) /* codec clk & FRM slave */
66#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */
67#define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */
68#define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */
69#define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */
70
71#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
72#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
73#define SND_SOC_DAIFMT_INV_MASK 0x0f00
74#define SND_SOC_DAIFMT_MASTER_MASK 0xf000
75
76/*
77 * Master Clock Directions

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71#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
72#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
73#define SND_SOC_DAIFMT_INV_MASK 0x0f00
74#define SND_SOC_DAIFMT_MASTER_MASK 0xf000
75
76/*
77 * Master Clock Directions

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