ocelot.h (62a22bcbd30ed01a0f0331288aa0cca9d9aae23b) ocelot.h (90e0aa8d108d22cb0dd646083fb3dfcc7a43a018)
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/* Copyright (c) 2017 Microsemi Corporation
3 */
4
5#ifndef _SOC_MSCC_OCELOT_H
6#define _SOC_MSCC_OCELOT_H
7
8#include <linux/ptp_clock_kernel.h>

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563 int pol_lpr;
564};
565
566struct ocelot_vlan {
567 bool valid;
568 u16 vid;
569};
570
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/* Copyright (c) 2017 Microsemi Corporation
3 */
4
5#ifndef _SOC_MSCC_OCELOT_H
6#define _SOC_MSCC_OCELOT_H
7
8#include <linux/ptp_clock_kernel.h>

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563 int pol_lpr;
564};
565
566struct ocelot_vlan {
567 bool valid;
568 u16 vid;
569};
570
571struct ocelot_bridge_vlan {
572 u16 vid;
573 unsigned long portmask;
574 struct list_head list;
575};
576
571enum ocelot_port_tag_config {
572 /* all VLANs are egress-untagged */
573 OCELOT_PORT_TAG_DISABLED = 0,
574 /* all VLANs except the native VLAN and VID 0 are egress-tagged */
575 OCELOT_PORT_TAG_NATIVE = 1,
576 /* all VLANs except VID 0 are egress-tagged */
577 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,
578 /* all VLANs are egress-tagged */

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641 int packet_buffer_size;
642 int num_frame_refs;
643 int num_mact_rows;
644
645 struct ocelot_port **ports;
646
647 u8 base_mac[ETH_ALEN];
648
577enum ocelot_port_tag_config {
578 /* all VLANs are egress-untagged */
579 OCELOT_PORT_TAG_DISABLED = 0,
580 /* all VLANs except the native VLAN and VID 0 are egress-tagged */
581 OCELOT_PORT_TAG_NATIVE = 1,
582 /* all VLANs except VID 0 are egress-tagged */
583 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,
584 /* all VLANs are egress-tagged */

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647 int packet_buffer_size;
648 int num_frame_refs;
649 int num_mact_rows;
650
651 struct ocelot_port **ports;
652
653 u8 base_mac[ETH_ALEN];
654
649 /* Keep track of the vlan port masks */
650 u32 vlan_mask[VLAN_N_VID];
655 struct list_head vlans;
651
652 /* Switches like VSC9959 have flooding per traffic class */
653 int num_flooding_pgids;
654
655 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
656 * the CPU is located after the physical ports (at the
657 * num_phys_ports index).
658 */

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657 /* Switches like VSC9959 have flooding per traffic class */
658 int num_flooding_pgids;
659
660 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
661 * the CPU is located after the physical ports (at the
662 * num_phys_ports index).
663 */

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