stmmac.h (d976a525c371276cebd2517349d1d3568a0e48b5) stmmac.h (19d9187317979cf0c25f67017d2676149abc46b2)
1/*******************************************************************************
2
3 Header file for stmmac platform data
4
5 Copyright (C) 2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,

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50/* MTL algorithms identifiers */
51#define MTL_TX_ALGORITHM_WRR 0x0
52#define MTL_TX_ALGORITHM_WFQ 0x1
53#define MTL_TX_ALGORITHM_DWRR 0x2
54#define MTL_TX_ALGORITHM_SP 0x3
55#define MTL_RX_ALGORITHM_SP 0x4
56#define MTL_RX_ALGORITHM_WSP 0x5
57
1/*******************************************************************************
2
3 Header file for stmmac platform data
4
5 Copyright (C) 2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,

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50/* MTL algorithms identifiers */
51#define MTL_TX_ALGORITHM_WRR 0x0
52#define MTL_TX_ALGORITHM_WFQ 0x1
53#define MTL_TX_ALGORITHM_DWRR 0x2
54#define MTL_TX_ALGORITHM_SP 0x3
55#define MTL_RX_ALGORITHM_SP 0x4
56#define MTL_RX_ALGORITHM_WSP 0x5
57
58/* RX Queue Mode */
59#define MTL_RX_DCB 0x0
60#define MTL_RX_AVB 0x1
58/* RX/TX Queue Mode */
59#define MTL_QUEUE_DCB 0x0
60#define MTL_QUEUE_AVB 0x1
61
62/* The MDC clock could be set higher than the IEEE 802.3
63 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
64 * of value different than the above defined values. The resultant MDIO
65 * clock frequency of 12.5 MHz is applicable for the interfacing chips
66 * supporting higher MDC clocks.
67 * The MDC clock selection macros need to be defined for MDC clock rate
68 * of 12.5 MHz, corresponding to the following selection.

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126
127struct stmmac_rxq_cfg {
128 u8 mode_to_use;
129 u8 chan;
130};
131
132struct stmmac_txq_cfg {
133 u8 weight;
61
62/* The MDC clock could be set higher than the IEEE 802.3
63 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
64 * of value different than the above defined values. The resultant MDIO
65 * clock frequency of 12.5 MHz is applicable for the interfacing chips
66 * supporting higher MDC clocks.
67 * The MDC clock selection macros need to be defined for MDC clock rate
68 * of 12.5 MHz, corresponding to the following selection.

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126
127struct stmmac_rxq_cfg {
128 u8 mode_to_use;
129 u8 chan;
130};
131
132struct stmmac_txq_cfg {
133 u8 weight;
134 u8 mode_to_use;
135 /* Credit Base Shaper parameters */
136 u32 send_slope;
137 u32 idle_slope;
138 u32 high_credit;
139 u32 low_credit;
134};
135
136struct plat_stmmacenet_data {
137 int bus_id;
138 int phy_addr;
139 int interface;
140 struct stmmac_mdio_bus_data *mdio_bus_data;
141 struct device_node *phy_node;

--- 40 unchanged lines hidden --- 		140};
141
142struct plat_stmmacenet_data {
143 int bus_id;
144 int phy_addr;
145 int interface;
146 struct stmmac_mdio_bus_data *mdio_bus_data;
147 struct device_node *phy_node;

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