| exynos850.h (f20f35f46f1a65e1c4b65d8fb62acdbdafd11e1e) | exynos850.h (8f3fc0ed70b97e7544ec1a57c60fe6b2f2f778c3) |
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| 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2/* 3 * Copyright (C) 2021 Linaro Ltd. 4 * Author: Sam Protsenko <semen.protsenko@linaro.org> 5 * 6 * Device Tree binding constants for Exynos850 clock controller. 7 */ 8 --- 59 unchanged lines hidden (view full) --- 68#define CLK_GOUT_IS_BUS 56 69#define CLK_GOUT_IS_ITP 57 70#define CLK_GOUT_IS_VRA 58 71#define CLK_GOUT_IS_GDC 59 72#define CLK_DOUT_IS_BUS 60 73#define CLK_DOUT_IS_ITP 61 74#define CLK_DOUT_IS_VRA 62 75#define CLK_DOUT_IS_GDC 63 | 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2/* 3 * Copyright (C) 2021 Linaro Ltd. 4 * Author: Sam Protsenko <semen.protsenko@linaro.org> 5 * 6 * Device Tree binding constants for Exynos850 clock controller. 7 */ 8 --- 59 unchanged lines hidden (view full) --- 68#define CLK_GOUT_IS_BUS 56 69#define CLK_GOUT_IS_ITP 57 70#define CLK_GOUT_IS_VRA 58 71#define CLK_GOUT_IS_GDC 59 72#define CLK_DOUT_IS_BUS 60 73#define CLK_DOUT_IS_ITP 61 74#define CLK_DOUT_IS_VRA 62 75#define CLK_DOUT_IS_GDC 63 |
| 76#define TOP_NR_CLK 64 | 76#define CLK_MOUT_MFCMSCL_MFC 64 77#define CLK_MOUT_MFCMSCL_M2M 65 78#define CLK_MOUT_MFCMSCL_MCSC 66 79#define CLK_MOUT_MFCMSCL_JPEG 67 80#define CLK_GOUT_MFCMSCL_MFC 68 81#define CLK_GOUT_MFCMSCL_M2M 69 82#define CLK_GOUT_MFCMSCL_MCSC 70 83#define CLK_GOUT_MFCMSCL_JPEG 71 84#define CLK_DOUT_MFCMSCL_MFC 72 85#define CLK_DOUT_MFCMSCL_M2M 73 86#define CLK_DOUT_MFCMSCL_MCSC 74 87#define CLK_DOUT_MFCMSCL_JPEG 75 88#define TOP_NR_CLK 76 |
| 77 78/* CMU_APM */ 79#define CLK_RCO_I3C_PMIC 1 80#define OSCCLK_RCO_APM 2 81#define CLK_RCO_APM__ALV 3 82#define CLK_DLL_DCO 4 83#define CLK_MOUT_APM_BUS_USER 5 84#define CLK_MOUT_RCO_APM_I3C_USER 6 --- 135 unchanged lines hidden (view full) --- 220#define CLK_GOUT_IS_PPMU_IS0_PCLK 18 221#define CLK_GOUT_IS_PPMU_IS1_ACLK 19 222#define CLK_GOUT_IS_PPMU_IS1_PCLK 20 223#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 224#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 225#define CLK_GOUT_IS_SYSREG_PCLK 23 226#define IS_NR_CLK 24 227 | 89 90/* CMU_APM */ 91#define CLK_RCO_I3C_PMIC 1 92#define OSCCLK_RCO_APM 2 93#define CLK_RCO_APM__ALV 3 94#define CLK_DLL_DCO 4 95#define CLK_MOUT_APM_BUS_USER 5 96#define CLK_MOUT_RCO_APM_I3C_USER 6 --- 135 unchanged lines hidden (view full) --- 232#define CLK_GOUT_IS_PPMU_IS0_PCLK 18 233#define CLK_GOUT_IS_PPMU_IS1_ACLK 19 234#define CLK_GOUT_IS_PPMU_IS1_PCLK 20 235#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 236#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 237#define CLK_GOUT_IS_SYSREG_PCLK 23 238#define IS_NR_CLK 24 239 |
| 240/* CMU_MFCMSCL */ 241#define CLK_MOUT_MFCMSCL_MFC_USER 1 242#define CLK_MOUT_MFCMSCL_M2M_USER 2 243#define CLK_MOUT_MFCMSCL_MCSC_USER 3 244#define CLK_MOUT_MFCMSCL_JPEG_USER 4 245#define CLK_DOUT_MFCMSCL_BUSP 5 246#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6 247#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7 248#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8 249#define CLK_GOUT_MFCMSCL_M2M_ACLK 9 250#define CLK_GOUT_MFCMSCL_MCSC_CLK 10 251#define CLK_GOUT_MFCMSCL_MFC_ACLK 11 252#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12 253#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 254#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 255#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 256#define MFCMSCL_NR_CLK 16 257 |
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| 228/* CMU_PERI */ 229#define CLK_MOUT_PERI_BUS_USER 1 230#define CLK_MOUT_PERI_UART_USER 2 231#define CLK_MOUT_PERI_HSI2C_USER 3 232#define CLK_MOUT_PERI_SPI_USER 4 233#define CLK_DOUT_PERI_HSI2C0 5 234#define CLK_DOUT_PERI_HSI2C1 6 235#define CLK_DOUT_PERI_HSI2C2 7 --- 60 unchanged lines hidden --- | 258/* CMU_PERI */ 259#define CLK_MOUT_PERI_BUS_USER 1 260#define CLK_MOUT_PERI_UART_USER 2 261#define CLK_MOUT_PERI_HSI2C_USER 3 262#define CLK_MOUT_PERI_SPI_USER 4 263#define CLK_DOUT_PERI_HSI2C0 5 264#define CLK_DOUT_PERI_HSI2C1 6 265#define CLK_DOUT_PERI_HSI2C2 7 --- 60 unchanged lines hidden --- |