| uhci-hcd.h (5a84d159061d914c8dd4aa372ac6e9529c2be453) | uhci-hcd.h (28b9325e6ae45ffb5e99fedcafe00f25fcaacf06) |
|---|---|
| 1#ifndef __LINUX_UHCI_HCD_H 2#define __LINUX_UHCI_HCD_H 3 4#include <linux/list.h> 5#include <linux/usb.h> 6 7#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) 8#define PIPE_DEVEP_MASK 0x0007ff00 --- 115 unchanged lines hidden (view full) --- 124#define QH_STATE_ACTIVE 3 /* QH is on the schedule */ 125 126struct uhci_qh { 127 /* Hardware fields */ 128 __le32 link; /* Next QH in the schedule */ 129 __le32 element; /* Queue element (TD) pointer */ 130 131 /* Software fields */ | 1#ifndef __LINUX_UHCI_HCD_H 2#define __LINUX_UHCI_HCD_H 3 4#include <linux/list.h> 5#include <linux/usb.h> 6 7#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) 8#define PIPE_DEVEP_MASK 0x0007ff00 --- 115 unchanged lines hidden (view full) --- 124#define QH_STATE_ACTIVE 3 /* QH is on the schedule */ 125 126struct uhci_qh { 127 /* Hardware fields */ 128 __le32 link; /* Next QH in the schedule */ 129 __le32 element; /* Queue element (TD) pointer */ 130 131 /* Software fields */ |
| 132 dma_addr_t dma_handle; 133 |
|
| 132 struct list_head node; /* Node in the list of QHs */ 133 struct usb_host_endpoint *hep; /* Endpoint information */ 134 struct usb_device *udev; 135 struct list_head queue; /* Queue of urbps for this QH */ 136 struct uhci_qh *skel; /* Skeleton for this QH */ 137 struct uhci_td *dummy_td; /* Dummy TD to end the queue */ 138 struct uhci_td *post_td; /* Last TD completed */ 139 --- 5 unchanged lines hidden (view full) --- 145 short phase; /* Between 0 and period-1 */ 146 short load; /* Periodic time requirement, in us */ 147 unsigned int iso_frame; /* Frame # for iso_packet_desc */ 148 int iso_status; /* Status for Isochronous URBs */ 149 150 int state; /* QH_STATE_xxx; see above */ 151 int type; /* Queue type (control, bulk, etc) */ 152 | 134 struct list_head node; /* Node in the list of QHs */ 135 struct usb_host_endpoint *hep; /* Endpoint information */ 136 struct usb_device *udev; 137 struct list_head queue; /* Queue of urbps for this QH */ 138 struct uhci_qh *skel; /* Skeleton for this QH */ 139 struct uhci_td *dummy_td; /* Dummy TD to end the queue */ 140 struct uhci_td *post_td; /* Last TD completed */ 141 --- 5 unchanged lines hidden (view full) --- 147 short phase; /* Between 0 and period-1 */ 148 short load; /* Periodic time requirement, in us */ 149 unsigned int iso_frame; /* Frame # for iso_packet_desc */ 150 int iso_status; /* Status for Isochronous URBs */ 151 152 int state; /* QH_STATE_xxx; see above */ 153 int type; /* Queue type (control, bulk, etc) */ 154 |
| 153 dma_addr_t dma_handle; 154 | |
| 155 unsigned int initial_toggle:1; /* Endpoint's current toggle value */ 156 unsigned int needs_fixup:1; /* Must fix the TD toggle values */ 157 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */ 158 unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */ 159 unsigned int bandwidth_reserved:1; /* Periodic bandwidth has 160 * been allocated */ 161} __attribute__((aligned(16))); 162 163/* 164 * We need a special accessor for the element pointer because it is 165 * subject to asynchronous updates by the controller. 166 */ 167static inline __le32 qh_element(struct uhci_qh *qh) { 168 __le32 element = qh->element; 169 170 barrier(); 171 return element; 172} 173 | 155 unsigned int initial_toggle:1; /* Endpoint's current toggle value */ 156 unsigned int needs_fixup:1; /* Must fix the TD toggle values */ 157 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */ 158 unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */ 159 unsigned int bandwidth_reserved:1; /* Periodic bandwidth has 160 * been allocated */ 161} __attribute__((aligned(16))); 162 163/* 164 * We need a special accessor for the element pointer because it is 165 * subject to asynchronous updates by the controller. 166 */ 167static inline __le32 qh_element(struct uhci_qh *qh) { 168 __le32 element = qh->element; 169 170 barrier(); 171 return element; 172} 173 |
| 174#define LINK_TO_QH(qh) (UHCI_PTR_QH | cpu_to_le32((qh)->dma_handle)) |
|
| 174 | 175 |
| 176 |
|
| 175/* 176 * Transfer Descriptors 177 */ 178 179/* 180 * for TD <status>: 181 */ 182#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ --- 76 unchanged lines hidden (view full) --- 259 */ 260static inline u32 td_status(struct uhci_td *td) { 261 __le32 status = td->status; 262 263 barrier(); 264 return le32_to_cpu(status); 265} 266 | 177/* 178 * Transfer Descriptors 179 */ 180 181/* 182 * for TD <status>: 183 */ 184#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ --- 76 unchanged lines hidden (view full) --- 261 */ 262static inline u32 td_status(struct uhci_td *td) { 263 __le32 status = td->status; 264 265 barrier(); 266 return le32_to_cpu(status); 267} 268 |
| 269#define LINK_TO_TD(td) (cpu_to_le32((td)->dma_handle)) |
|
| 267 | 270 |
| 271 |
|
| 268/* 269 * Skeleton Queue Headers 270 */ 271 272/* 273 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for 274 * automatic queuing. To make it easy to insert entries into the schedule, 275 * we have a skeleton of QHs for each predefined Interrupt latency, --- 203 unchanged lines hidden --- | 272/* 273 * Skeleton Queue Headers 274 */ 275 276/* 277 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for 278 * automatic queuing. To make it easy to insert entries into the schedule, 279 * we have a skeleton of QHs for each predefined Interrupt latency, --- 203 unchanged lines hidden --- |