| hw.h (d14ccaba8dc7aa1f137ef93349b08196ce0f0347) | hw.h (66e77a24a8c36ff83f0a12f44d23d8141e82fa3b) |
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| 1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * hw.h - DesignWare HS OTG Controller hardware definitions 4 * 5 * Copyright 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 296 unchanged lines hidden (view full) --- 305#define GHWCFG4_B_VALID_FILT_EN BIT(23) 306#define GHWCFG4_A_VALID_FILT_EN BIT(22) 307#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21) 308#define GHWCFG4_IDDIG_FILT_EN BIT(20) 309#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) 310#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 311#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) 312#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 | 1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * hw.h - DesignWare HS OTG Controller hardware definitions 4 * 5 * Copyright 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 296 unchanged lines hidden (view full) --- 305#define GHWCFG4_B_VALID_FILT_EN BIT(23) 306#define GHWCFG4_A_VALID_FILT_EN BIT(22) 307#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21) 308#define GHWCFG4_IDDIG_FILT_EN BIT(20) 309#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) 310#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 311#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) 312#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 |
| 313#define GHWCFG4_ACG_SUPPORTED BIT(12) |
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| 313#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 314#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 315#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 316#define GHWCFG4_XHIBER BIT(7) 317#define GHWCFG4_HIBER BIT(6) 318#define GHWCFG4_MIN_AHB_FREQ BIT(5) 319#define GHWCFG4_POWER_OPTIMIZ BIT(4) 320#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) --- 319 unchanged lines hidden (view full) --- 640#define PCGCTL_DEEP_SLEEP BIT(7) 641#define PCGCTL_PHY_IN_SLEEP BIT(6) 642#define PCGCTL_ENBL_SLEEP_GATING BIT(5) 643#define PCGCTL_RSTPDWNMODULE BIT(3) 644#define PCGCTL_PWRCLMP BIT(2) 645#define PCGCTL_GATEHCLK BIT(1) 646#define PCGCTL_STOPPCLK BIT(0) 647 | 314#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 315#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 316#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 317#define GHWCFG4_XHIBER BIT(7) 318#define GHWCFG4_HIBER BIT(6) 319#define GHWCFG4_MIN_AHB_FREQ BIT(5) 320#define GHWCFG4_POWER_OPTIMIZ BIT(4) 321#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) --- 319 unchanged lines hidden (view full) --- 641#define PCGCTL_DEEP_SLEEP BIT(7) 642#define PCGCTL_PHY_IN_SLEEP BIT(6) 643#define PCGCTL_ENBL_SLEEP_GATING BIT(5) 644#define PCGCTL_RSTPDWNMODULE BIT(3) 645#define PCGCTL_PWRCLMP BIT(2) 646#define PCGCTL_GATEHCLK BIT(1) 647#define PCGCTL_STOPPCLK BIT(0) 648 |
| 649#define PCGCCTL1 HSOTG_REG(0xe04) 650#define PCGCCTL1_TIMER (0x3 << 1) 651#define PCGCCTL1_GATEEN BIT(0) 652 |
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| 648#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) 649 650/* Host Mode Registers */ 651 652#define HCFG HSOTG_REG(0x0400) 653#define HCFG_MODECHTIMEN BIT(31) 654#define HCFG_PERSCHEDENA BIT(26) 655#define HCFG_FRLISTEN_MASK (0x3 << 24) --- 214 unchanged lines hidden --- | 653#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) 654 655/* Host Mode Registers */ 656 657#define HCFG HSOTG_REG(0x0400) 658#define HCFG_MODECHTIMEN BIT(31) 659#define HCFG_PERSCHEDENA BIT(26) 660#define HCFG_FRLISTEN_MASK (0x3 << 24) --- 214 unchanged lines hidden --- |