| cdnsp-mem.c (dc68ba6c72366e0402fbcc4783a8b6ab610265df) | cdnsp-mem.c (e2d60f8c475a4955b8c39bda4cf6b10b09460772) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Cadence CDNSP DRD Driver. 4 * 5 * Copyright (C) 2020 Cadence. 6 * 7 * Author: Pawel Laszczak <pawell@cadence.com> 8 * --- 1214 unchanged lines hidden (view full) --- 1223 1224 /* 1225 * Doorbell array must be physically contiguous 1226 * and 64-byte (cache line) aligned. 1227 */ 1228 pdev->dcbaa = dma_alloc_coherent(dev, sizeof(*pdev->dcbaa), 1229 &dma, GFP_KERNEL); 1230 if (!pdev->dcbaa) | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Cadence CDNSP DRD Driver. 4 * 5 * Copyright (C) 2020 Cadence. 6 * 7 * Author: Pawel Laszczak <pawell@cadence.com> 8 * --- 1214 unchanged lines hidden (view full) --- 1223 1224 /* 1225 * Doorbell array must be physically contiguous 1226 * and 64-byte (cache line) aligned. 1227 */ 1228 pdev->dcbaa = dma_alloc_coherent(dev, sizeof(*pdev->dcbaa), 1229 &dma, GFP_KERNEL); 1230 if (!pdev->dcbaa) |
| 1231 goto mem_init_fail; | 1231 return -ENOMEM; |
| 1232 1233 memset(pdev->dcbaa, 0, sizeof(*pdev->dcbaa)); 1234 pdev->dcbaa->dma = dma; 1235 1236 cdnsp_write_64(dma, &pdev->op_regs->dcbaa_ptr); 1237 1238 /* 1239 * Initialize the ring segment pool. The ring must be a contiguous 1240 * structure comprised of TRBs. The TRBs must be 16 byte aligned, 1241 * however, the command ring segment needs 64-byte aligned segments 1242 * and our use of dma addresses in the trb_address_map radix tree needs 1243 * TRB_SEGMENT_SIZE alignment, so driver pick the greater alignment 1244 * need. 1245 */ 1246 pdev->segment_pool = dma_pool_create("CDNSP ring segments", dev, 1247 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, 1248 page_size); | 1232 1233 memset(pdev->dcbaa, 0, sizeof(*pdev->dcbaa)); 1234 pdev->dcbaa->dma = dma; 1235 1236 cdnsp_write_64(dma, &pdev->op_regs->dcbaa_ptr); 1237 1238 /* 1239 * Initialize the ring segment pool. The ring must be a contiguous 1240 * structure comprised of TRBs. The TRBs must be 16 byte aligned, 1241 * however, the command ring segment needs 64-byte aligned segments 1242 * and our use of dma addresses in the trb_address_map radix tree needs 1243 * TRB_SEGMENT_SIZE alignment, so driver pick the greater alignment 1244 * need. 1245 */ 1246 pdev->segment_pool = dma_pool_create("CDNSP ring segments", dev, 1247 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, 1248 page_size); |
| 1249 if (!pdev->segment_pool) 1250 goto release_dcbaa; |
|
| 1249 1250 pdev->device_pool = dma_pool_create("CDNSP input/output contexts", dev, 1251 CDNSP_CTX_SIZE, 64, page_size); | 1251 1252 pdev->device_pool = dma_pool_create("CDNSP input/output contexts", dev, 1253 CDNSP_CTX_SIZE, 64, page_size); |
| 1254 if (!pdev->device_pool) 1255 goto destroy_segment_pool; |
|
| 1252 | 1256 |
| 1253 if (!pdev->segment_pool || !pdev->device_pool) 1254 goto mem_init_fail; | |
| 1255 1256 /* Set up the command ring to have one segments for now. */ 1257 pdev->cmd_ring = cdnsp_ring_alloc(pdev, 1, TYPE_COMMAND, 0, GFP_KERNEL); 1258 if (!pdev->cmd_ring) | 1257 1258 /* Set up the command ring to have one segments for now. */ 1259 pdev->cmd_ring = cdnsp_ring_alloc(pdev, 1, TYPE_COMMAND, 0, GFP_KERNEL); 1260 if (!pdev->cmd_ring) |
| 1259 goto mem_init_fail; | 1261 goto destroy_device_pool; |
| 1260 1261 /* Set the address in the Command Ring Control register */ 1262 val_64 = cdnsp_read_64(&pdev->op_regs->cmd_ring); 1263 val_64 = (val_64 & (u64)CMD_RING_RSVD_BITS) | 1264 (pdev->cmd_ring->first_seg->dma & (u64)~CMD_RING_RSVD_BITS) | 1265 pdev->cmd_ring->cycle_state; 1266 cdnsp_write_64(val_64, &pdev->op_regs->cmd_ring); 1267 --- 6 unchanged lines hidden (view full) --- 1274 1275 /* 1276 * Event ring setup: Allocate a normal ring, but also setup 1277 * the event ring segment table (ERST). 1278 */ 1279 pdev->event_ring = cdnsp_ring_alloc(pdev, ERST_NUM_SEGS, TYPE_EVENT, 1280 0, GFP_KERNEL); 1281 if (!pdev->event_ring) | 1262 1263 /* Set the address in the Command Ring Control register */ 1264 val_64 = cdnsp_read_64(&pdev->op_regs->cmd_ring); 1265 val_64 = (val_64 & (u64)CMD_RING_RSVD_BITS) | 1266 (pdev->cmd_ring->first_seg->dma & (u64)~CMD_RING_RSVD_BITS) | 1267 pdev->cmd_ring->cycle_state; 1268 cdnsp_write_64(val_64, &pdev->op_regs->cmd_ring); 1269 --- 6 unchanged lines hidden (view full) --- 1276 1277 /* 1278 * Event ring setup: Allocate a normal ring, but also setup 1279 * the event ring segment table (ERST). 1280 */ 1281 pdev->event_ring = cdnsp_ring_alloc(pdev, ERST_NUM_SEGS, TYPE_EVENT, 1282 0, GFP_KERNEL); 1283 if (!pdev->event_ring) |
| 1282 goto mem_init_fail; | 1284 goto free_cmd_ring; |
| 1283 1284 ret = cdnsp_alloc_erst(pdev, pdev->event_ring, &pdev->erst); 1285 if (ret) | 1285 1286 ret = cdnsp_alloc_erst(pdev, pdev->event_ring, &pdev->erst); 1287 if (ret) |
| 1286 goto mem_init_fail; | 1288 goto free_event_ring; |
| 1287 1288 /* Set ERST count with the number of entries in the segment table. */ 1289 val = readl(&pdev->ir_set->erst_size); 1290 val &= ERST_SIZE_MASK; 1291 val |= ERST_NUM_SEGS; 1292 writel(val, &pdev->ir_set->erst_size); 1293 1294 /* Set the segment table base address. */ 1295 val_64 = cdnsp_read_64(&pdev->ir_set->erst_base); 1296 val_64 &= ERST_PTR_MASK; 1297 val_64 |= (pdev->erst.erst_dma_addr & (u64)~ERST_PTR_MASK); 1298 cdnsp_write_64(val_64, &pdev->ir_set->erst_base); 1299 1300 /* Set the event ring dequeue address. */ 1301 cdnsp_set_event_deq(pdev); 1302 1303 ret = cdnsp_setup_port_arrays(pdev); 1304 if (ret) | 1289 1290 /* Set ERST count with the number of entries in the segment table. */ 1291 val = readl(&pdev->ir_set->erst_size); 1292 val &= ERST_SIZE_MASK; 1293 val |= ERST_NUM_SEGS; 1294 writel(val, &pdev->ir_set->erst_size); 1295 1296 /* Set the segment table base address. */ 1297 val_64 = cdnsp_read_64(&pdev->ir_set->erst_base); 1298 val_64 &= ERST_PTR_MASK; 1299 val_64 |= (pdev->erst.erst_dma_addr & (u64)~ERST_PTR_MASK); 1300 cdnsp_write_64(val_64, &pdev->ir_set->erst_base); 1301 1302 /* Set the event ring dequeue address. */ 1303 cdnsp_set_event_deq(pdev); 1304 1305 ret = cdnsp_setup_port_arrays(pdev); 1306 if (ret) |
| 1305 goto mem_init_fail; | 1307 goto free_erst; |
| 1306 1307 ret = cdnsp_alloc_priv_device(pdev); 1308 if (ret) { 1309 dev_err(pdev->dev, 1310 "Could not allocate cdnsp_device data structures\n"); | 1308 1309 ret = cdnsp_alloc_priv_device(pdev); 1310 if (ret) { 1311 dev_err(pdev->dev, 1312 "Could not allocate cdnsp_device data structures\n"); |
| 1311 goto mem_init_fail; | 1313 goto free_erst; |
| 1312 } 1313 1314 return 0; 1315 | 1314 } 1315 1316 return 0; 1317 |
| 1316mem_init_fail: 1317 dev_err(pdev->dev, "Couldn't initialize memory\n"); 1318 cdnsp_halt(pdev); | 1318free_erst: 1319 cdnsp_free_erst(pdev, &pdev->erst); 1320free_event_ring: 1321 cdnsp_ring_free(pdev, pdev->event_ring); 1322free_cmd_ring: 1323 cdnsp_ring_free(pdev, pdev->cmd_ring); 1324destroy_device_pool: 1325 dma_pool_destroy(pdev->device_pool); 1326destroy_segment_pool: 1327 dma_pool_destroy(pdev->segment_pool); 1328release_dcbaa: 1329 dma_free_coherent(dev, sizeof(*pdev->dcbaa), pdev->dcbaa, 1330 pdev->dcbaa->dma); 1331 |
| 1319 cdnsp_reset(pdev); | 1332 cdnsp_reset(pdev); |
| 1320 cdnsp_mem_cleanup(pdev); | |
| 1321 1322 return ret; 1323} | 1333 1334 return ret; 1335} |