cdnsp-mem.c (118b2a3237cf499727649b1c018dd2f1d329af08) cdnsp-mem.c (dc68ba6c72366e0402fbcc4783a8b6ab610265df)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence CDNSP DRD Driver.
4 *
5 * Copyright (C) 2020 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 *

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679 if (pdev->out_ctx.bytes)
680 dma_pool_free(pdev->device_pool, pdev->out_ctx.bytes,
681 pdev->out_ctx.dma);
682
683 pdev->in_ctx.bytes = NULL;
684 pdev->out_ctx.bytes = NULL;
685}
686
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence CDNSP DRD Driver.
4 *
5 * Copyright (C) 2020 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 *

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679 if (pdev->out_ctx.bytes)
680 dma_pool_free(pdev->device_pool, pdev->out_ctx.bytes,
681 pdev->out_ctx.dma);
682
683 pdev->in_ctx.bytes = NULL;
684 pdev->out_ctx.bytes = NULL;
685}
686
687static int cdnsp_alloc_priv_device(struct cdnsp_device *pdev, gfp_t flags)
687static int cdnsp_alloc_priv_device(struct cdnsp_device *pdev)
688{
689 int ret = -ENOMEM;
690
691 ret = cdnsp_init_device_ctx(pdev);
692 if (ret)
693 return ret;
694
695 /* Allocate endpoint 0 ring. */
688{
689 int ret = -ENOMEM;
690
691 ret = cdnsp_init_device_ctx(pdev);
692 if (ret)
693 return ret;
694
695 /* Allocate endpoint 0 ring. */
696 pdev->eps[0].ring = cdnsp_ring_alloc(pdev, 2, TYPE_CTRL, 0, flags);
696 pdev->eps[0].ring = cdnsp_ring_alloc(pdev, 2, TYPE_CTRL, 0, GFP_ATOMIC);
697 if (!pdev->eps[0].ring)
698 goto fail;
699
700 /* Point to output device context in dcbaa. */
701 pdev->dcbaa->dev_context_ptrs[1] = cpu_to_le64(pdev->out_ctx.dma);
702 pdev->cmd.in_ctx = &pdev->in_ctx;
703
704 trace_cdnsp_alloc_priv_device(pdev);

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1015 pep->in_ctx->ep_info = 0;
1016 pep->in_ctx->ep_info2 = 0;
1017 pep->in_ctx->deq = 0;
1018 pep->in_ctx->tx_info = 0;
1019}
1020
1021static int cdnsp_alloc_erst(struct cdnsp_device *pdev,
1022 struct cdnsp_ring *evt_ring,
697 if (!pdev->eps[0].ring)
698 goto fail;
699
700 /* Point to output device context in dcbaa. */
701 pdev->dcbaa->dev_context_ptrs[1] = cpu_to_le64(pdev->out_ctx.dma);
702 pdev->cmd.in_ctx = &pdev->in_ctx;
703
704 trace_cdnsp_alloc_priv_device(pdev);

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1015 pep->in_ctx->ep_info = 0;
1016 pep->in_ctx->ep_info2 = 0;
1017 pep->in_ctx->deq = 0;
1018 pep->in_ctx->tx_info = 0;
1019}
1020
1021static int cdnsp_alloc_erst(struct cdnsp_device *pdev,
1022 struct cdnsp_ring *evt_ring,
1023 struct cdnsp_erst *erst,
1024 gfp_t flags)
1023 struct cdnsp_erst *erst)
1025{
1026 struct cdnsp_erst_entry *entry;
1027 struct cdnsp_segment *seg;
1028 unsigned int val;
1029 size_t size;
1030
1031 size = sizeof(struct cdnsp_erst_entry) * evt_ring->num_segs;
1032 erst->entries = dma_alloc_coherent(pdev->dev, size,
1024{
1025 struct cdnsp_erst_entry *entry;
1026 struct cdnsp_segment *seg;
1027 unsigned int val;
1028 size_t size;
1029
1030 size = sizeof(struct cdnsp_erst_entry) * evt_ring->num_segs;
1031 erst->entries = dma_alloc_coherent(pdev->dev, size,
1033 &erst->erst_dma_addr, flags);
1032 &erst->erst_dma_addr, GFP_KERNEL);
1034 if (!erst->entries)
1035 return -ENOMEM;
1036
1037 erst->num_entries = evt_ring->num_segs;
1038
1039 seg = evt_ring->first_seg;
1040 for (val = 0; val < evt_ring->num_segs; val++) {
1041 entry = &erst->entries[val];

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1137 port->port_num = port_offset;
1138 port->exist = 1;
1139}
1140
1141/*
1142 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
1143 * specify what speeds each port is supposed to be.
1144 */
1033 if (!erst->entries)
1034 return -ENOMEM;
1035
1036 erst->num_entries = evt_ring->num_segs;
1037
1038 seg = evt_ring->first_seg;
1039 for (val = 0; val < evt_ring->num_segs; val++) {
1040 entry = &erst->entries[val];

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1136 port->port_num = port_offset;
1137 port->exist = 1;
1138}
1139
1140/*
1141 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
1142 * specify what speeds each port is supposed to be.
1143 */
1145static int cdnsp_setup_port_arrays(struct cdnsp_device *pdev, gfp_t flags)
1144static int cdnsp_setup_port_arrays(struct cdnsp_device *pdev)
1146{
1147 void __iomem *base;
1148 u32 offset;
1149 int i;
1150
1151 base = &pdev->cap_regs->hc_capbase;
1152 offset = cdnsp_find_next_ext_cap(base, 0,
1153 EXT_CAP_CFG_DEV_20PORT_CAP_ID);

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1198
1199/*
1200 * Initialize memory for CDNSP (one-time init).
1201 *
1202 * Program the PAGESIZE register, initialize the device context array, create
1203 * device contexts, set up a command ring segment, create event
1204 * ring (one for now).
1205 */
1145{
1146 void __iomem *base;
1147 u32 offset;
1148 int i;
1149
1150 base = &pdev->cap_regs->hc_capbase;
1151 offset = cdnsp_find_next_ext_cap(base, 0,
1152 EXT_CAP_CFG_DEV_20PORT_CAP_ID);

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1197
1198/*
1199 * Initialize memory for CDNSP (one-time init).
1200 *
1201 * Program the PAGESIZE register, initialize the device context array, create
1202 * device contexts, set up a command ring segment, create event
1203 * ring (one for now).
1204 */
1206int cdnsp_mem_init(struct cdnsp_device *pdev, gfp_t flags)
1205int cdnsp_mem_init(struct cdnsp_device *pdev)
1207{
1208 struct device *dev = pdev->dev;
1209 int ret = -ENOMEM;
1210 unsigned int val;
1211 dma_addr_t dma;
1212 u32 page_size;
1213 u64 val_64;
1214

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1250
1251 pdev->device_pool = dma_pool_create("CDNSP input/output contexts", dev,
1252 CDNSP_CTX_SIZE, 64, page_size);
1253
1254 if (!pdev->segment_pool || !pdev->device_pool)
1255 goto mem_init_fail;
1256
1257 /* Set up the command ring to have one segments for now. */
1206{
1207 struct device *dev = pdev->dev;
1208 int ret = -ENOMEM;
1209 unsigned int val;
1210 dma_addr_t dma;
1211 u32 page_size;
1212 u64 val_64;
1213

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1249
1250 pdev->device_pool = dma_pool_create("CDNSP input/output contexts", dev,
1251 CDNSP_CTX_SIZE, 64, page_size);
1252
1253 if (!pdev->segment_pool || !pdev->device_pool)
1254 goto mem_init_fail;
1255
1256 /* Set up the command ring to have one segments for now. */
1258 pdev->cmd_ring = cdnsp_ring_alloc(pdev, 1, TYPE_COMMAND, 0, flags);
1257 pdev->cmd_ring = cdnsp_ring_alloc(pdev, 1, TYPE_COMMAND, 0, GFP_KERNEL);
1259 if (!pdev->cmd_ring)
1260 goto mem_init_fail;
1261
1262 /* Set the address in the Command Ring Control register */
1263 val_64 = cdnsp_read_64(&pdev->op_regs->cmd_ring);
1264 val_64 = (val_64 & (u64)CMD_RING_RSVD_BITS) |
1265 (pdev->cmd_ring->first_seg->dma & (u64)~CMD_RING_RSVD_BITS) |
1266 pdev->cmd_ring->cycle_state;

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1273 /* Set ir_set to interrupt register set 0 */
1274 pdev->ir_set = &pdev->run_regs->ir_set[0];
1275
1276 /*
1277 * Event ring setup: Allocate a normal ring, but also setup
1278 * the event ring segment table (ERST).
1279 */
1280 pdev->event_ring = cdnsp_ring_alloc(pdev, ERST_NUM_SEGS, TYPE_EVENT,
1258 if (!pdev->cmd_ring)
1259 goto mem_init_fail;
1260
1261 /* Set the address in the Command Ring Control register */
1262 val_64 = cdnsp_read_64(&pdev->op_regs->cmd_ring);
1263 val_64 = (val_64 & (u64)CMD_RING_RSVD_BITS) |
1264 (pdev->cmd_ring->first_seg->dma & (u64)~CMD_RING_RSVD_BITS) |
1265 pdev->cmd_ring->cycle_state;

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1272 /* Set ir_set to interrupt register set 0 */
1273 pdev->ir_set = &pdev->run_regs->ir_set[0];
1274
1275 /*
1276 * Event ring setup: Allocate a normal ring, but also setup
1277 * the event ring segment table (ERST).
1278 */
1279 pdev->event_ring = cdnsp_ring_alloc(pdev, ERST_NUM_SEGS, TYPE_EVENT,
1281 0, flags);
1280 0, GFP_KERNEL);
1282 if (!pdev->event_ring)
1283 goto mem_init_fail;
1284
1281 if (!pdev->event_ring)
1282 goto mem_init_fail;
1283
1285 ret = cdnsp_alloc_erst(pdev, pdev->event_ring, &pdev->erst, flags);
1284 ret = cdnsp_alloc_erst(pdev, pdev->event_ring, &pdev->erst);
1286 if (ret)
1287 goto mem_init_fail;
1288
1289 /* Set ERST count with the number of entries in the segment table. */
1290 val = readl(&pdev->ir_set->erst_size);
1291 val &= ERST_SIZE_MASK;
1292 val |= ERST_NUM_SEGS;
1293 writel(val, &pdev->ir_set->erst_size);
1294
1295 /* Set the segment table base address. */
1296 val_64 = cdnsp_read_64(&pdev->ir_set->erst_base);
1297 val_64 &= ERST_PTR_MASK;
1298 val_64 |= (pdev->erst.erst_dma_addr & (u64)~ERST_PTR_MASK);
1299 cdnsp_write_64(val_64, &pdev->ir_set->erst_base);
1300
1301 /* Set the event ring dequeue address. */
1302 cdnsp_set_event_deq(pdev);
1303
1285 if (ret)
1286 goto mem_init_fail;
1287
1288 /* Set ERST count with the number of entries in the segment table. */
1289 val = readl(&pdev->ir_set->erst_size);
1290 val &= ERST_SIZE_MASK;
1291 val |= ERST_NUM_SEGS;
1292 writel(val, &pdev->ir_set->erst_size);
1293
1294 /* Set the segment table base address. */
1295 val_64 = cdnsp_read_64(&pdev->ir_set->erst_base);
1296 val_64 &= ERST_PTR_MASK;
1297 val_64 |= (pdev->erst.erst_dma_addr & (u64)~ERST_PTR_MASK);
1298 cdnsp_write_64(val_64, &pdev->ir_set->erst_base);
1299
1300 /* Set the event ring dequeue address. */
1301 cdnsp_set_event_deq(pdev);
1302
1304 ret = cdnsp_setup_port_arrays(pdev, flags);
1303 ret = cdnsp_setup_port_arrays(pdev);
1305 if (ret)
1306 goto mem_init_fail;
1307
1304 if (ret)
1305 goto mem_init_fail;
1306
1308 ret = cdnsp_alloc_priv_device(pdev, GFP_ATOMIC);
1307 ret = cdnsp_alloc_priv_device(pdev);
1309 if (ret) {
1310 dev_err(pdev->dev,
1311 "Could not allocate cdnsp_device data structures\n");
1312 goto mem_init_fail;
1313 }
1314
1315 return 0;
1316
1317mem_init_fail:
1318 dev_err(pdev->dev, "Couldn't initialize memory\n");
1319 cdnsp_halt(pdev);
1320 cdnsp_reset(pdev);
1321 cdnsp_mem_cleanup(pdev);
1322
1323 return ret;
1324}
1308 if (ret) {
1309 dev_err(pdev->dev,
1310 "Could not allocate cdnsp_device data structures\n");
1311 goto mem_init_fail;
1312 }
1313
1314 return 0;
1315
1316mem_init_fail:
1317 dev_err(pdev->dev, "Couldn't initialize memory\n");
1318 cdnsp_halt(pdev);
1319 cdnsp_reset(pdev);
1320 cdnsp_mem_cleanup(pdev);
1321
1322 return ret;
1323}