stm32-usart.h (f8bade6c9a6213c2c5ba6e5bf32415ecab6e41e5) stm32-usart.h (3d530017bef1de7f7773eb9d3c65fbce924894a2)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald_baeza@yahoo.fr>
7 */
8

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122#define USART_SR_CMF BIT(17) /* F7 */
123#define USART_SR_SBKF BIT(18) /* F7 */
124#define USART_SR_WUF BIT(20) /* H7 */
125#define USART_SR_TEACK BIT(21) /* F7 */
126#define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_FE | USART_SR_PE)
127/* Dummy bits */
128#define USART_SR_DUMMY_RX BIT(16)
129
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald_baeza@yahoo.fr>
7 */
8

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122#define USART_SR_CMF BIT(17) /* F7 */
123#define USART_SR_SBKF BIT(18) /* F7 */
124#define USART_SR_WUF BIT(20) /* H7 */
125#define USART_SR_TEACK BIT(21) /* F7 */
126#define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_FE | USART_SR_PE)
127/* Dummy bits */
128#define USART_SR_DUMMY_RX BIT(16)
129
130/* USART_ICR (F7) */
131#define USART_CR_TC BIT(6)
132
133/* USART_DR */
134#define USART_DR_MASK GENMASK(8, 0)
135
136/* USART_BRR */
137#define USART_BRR_DIV_F_MASK GENMASK(3, 0)
138#define USART_BRR_DIV_M_MASK GENMASK(15, 4)
139#define USART_BRR_DIV_M_SHIFT 4
140#define USART_BRR_04_R_SHIFT 1

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267 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
268 unsigned char *tx_buf; /* dma tx buffer cpu address */
269 u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */
270 u32 cr3_irq; /* USART_CR3_RXFTIE */
271 int last_res;
272 bool tx_dma_busy; /* dma tx busy */
273 bool hw_flow_control;
274 bool fifoen;
130/* USART_DR */
131#define USART_DR_MASK GENMASK(8, 0)
132
133/* USART_BRR */
134#define USART_BRR_DIV_F_MASK GENMASK(3, 0)
135#define USART_BRR_DIV_M_MASK GENMASK(15, 4)
136#define USART_BRR_DIV_M_SHIFT 4
137#define USART_BRR_04_R_SHIFT 1

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264 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
265 unsigned char *tx_buf; /* dma tx buffer cpu address */
266 u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */
267 u32 cr3_irq; /* USART_CR3_RXFTIE */
268 int last_res;
269 bool tx_dma_busy; /* dma tx busy */
270 bool hw_flow_control;
271 bool fifoen;
275 int wakeirq;
272 bool wakeup_src;
276 int rdr_mask; /* receive data register mask */
277 struct mctrl_gpios *gpios; /* modem control gpios */
278};
279
280static struct stm32_port stm32_ports[STM32_MAX_PORTS];
281static struct uart_driver stm32_usart_driver;
273 int rdr_mask; /* receive data register mask */
274 struct mctrl_gpios *gpios; /* modem control gpios */
275};
276
277static struct stm32_port stm32_ports[STM32_MAX_PORTS];
278static struct uart_driver stm32_usart_driver;