stm32-usart.h (cc7aefd4fa6c0e12301a923b629f49bfbaaac6b1) stm32-usart.h (270e5a74fe4c78a857d65f1a129d3d77a36b8d58)
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald_baeza@yahoo.fr>
6 * License terms: GNU General Public License (GPL), version 2
7 */
8

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20 u8 icr;
21 u8 rdr;
22 u8 tdr;
23};
24
25struct stm32_usart_config {
26 u8 uart_enable_bit; /* USART_CR1_UE */
27 bool has_7bits_data;
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald_baeza@yahoo.fr>
6 * License terms: GNU General Public License (GPL), version 2
7 */
8

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20 u8 icr;
21 u8 rdr;
22 u8 tdr;
23};
24
25struct stm32_usart_config {
26 u8 uart_enable_bit; /* USART_CR1_UE */
27 bool has_7bits_data;
28 bool has_wakeup;
28};
29
30struct stm32_usart_info {
31 struct stm32_usart_offsets ofs;
32 struct stm32_usart_config cfg;
33};
34
35#define UNDEF_REG 0xff

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70 .tdr = 0x28,
71 },
72 .cfg = {
73 .uart_enable_bit = 0,
74 .has_7bits_data = true,
75 }
76};
77
29};
30
31struct stm32_usart_info {
32 struct stm32_usart_offsets ofs;
33 struct stm32_usart_config cfg;
34};
35
36#define UNDEF_REG 0xff

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71 .tdr = 0x28,
72 },
73 .cfg = {
74 .uart_enable_bit = 0,
75 .has_7bits_data = true,
76 }
77};
78
79struct stm32_usart_info stm32h7_info = {
80 .ofs = {
81 .cr1 = 0x00,
82 .cr2 = 0x04,
83 .cr3 = 0x08,
84 .brr = 0x0c,
85 .gtpr = 0x10,
86 .rtor = 0x14,
87 .rqr = 0x18,
88 .isr = 0x1c,
89 .icr = 0x20,
90 .rdr = 0x24,
91 .tdr = 0x28,
92 },
93 .cfg = {
94 .uart_enable_bit = 0,
95 .has_7bits_data = true,
96 .has_wakeup = true,
97 }
98};
99
78/* USART_SR (F4) / USART_ISR (F7) */
79#define USART_SR_PE BIT(0)
80#define USART_SR_FE BIT(1)
81#define USART_SR_NF BIT(2)
82#define USART_SR_ORE BIT(3)
83#define USART_SR_IDLE BIT(4)
84#define USART_SR_RXNE BIT(5)
85#define USART_SR_TC BIT(6)
86#define USART_SR_TXE BIT(7)
87#define USART_SR_LBD BIT(8)
88#define USART_SR_CTSIF BIT(9)
89#define USART_SR_CTS BIT(10) /* F7 */
90#define USART_SR_RTOF BIT(11) /* F7 */
91#define USART_SR_EOBF BIT(12) /* F7 */
92#define USART_SR_ABRE BIT(14) /* F7 */
93#define USART_SR_ABRF BIT(15) /* F7 */
94#define USART_SR_BUSY BIT(16) /* F7 */
95#define USART_SR_CMF BIT(17) /* F7 */
96#define USART_SR_SBKF BIT(18) /* F7 */
100/* USART_SR (F4) / USART_ISR (F7) */
101#define USART_SR_PE BIT(0)
102#define USART_SR_FE BIT(1)
103#define USART_SR_NF BIT(2)
104#define USART_SR_ORE BIT(3)
105#define USART_SR_IDLE BIT(4)
106#define USART_SR_RXNE BIT(5)
107#define USART_SR_TC BIT(6)
108#define USART_SR_TXE BIT(7)
109#define USART_SR_LBD BIT(8)
110#define USART_SR_CTSIF BIT(9)
111#define USART_SR_CTS BIT(10) /* F7 */
112#define USART_SR_RTOF BIT(11) /* F7 */
113#define USART_SR_EOBF BIT(12) /* F7 */
114#define USART_SR_ABRE BIT(14) /* F7 */
115#define USART_SR_ABRF BIT(15) /* F7 */
116#define USART_SR_BUSY BIT(16) /* F7 */
117#define USART_SR_CMF BIT(17) /* F7 */
118#define USART_SR_SBKF BIT(18) /* F7 */
119#define USART_SR_WUF BIT(20) /* H7 */
97#define USART_SR_TEACK BIT(21) /* F7 */
98#define USART_SR_ERR_MASK (USART_SR_LBD | USART_SR_ORE | \
99 USART_SR_FE | USART_SR_PE)
100/* Dummy bits */
101#define USART_SR_DUMMY_RX BIT(16)
102
103/* USART_ICR (F7) */
104#define USART_CR_TC BIT(6)

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109/* USART_BRR */
110#define USART_BRR_DIV_F_MASK GENMASK(3, 0)
111#define USART_BRR_DIV_M_MASK GENMASK(15, 4)
112#define USART_BRR_DIV_M_SHIFT 4
113
114/* USART_CR1 */
115#define USART_CR1_SBK BIT(0)
116#define USART_CR1_RWU BIT(1) /* F4 */
120#define USART_SR_TEACK BIT(21) /* F7 */
121#define USART_SR_ERR_MASK (USART_SR_LBD | USART_SR_ORE | \
122 USART_SR_FE | USART_SR_PE)
123/* Dummy bits */
124#define USART_SR_DUMMY_RX BIT(16)
125
126/* USART_ICR (F7) */
127#define USART_CR_TC BIT(6)

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132/* USART_BRR */
133#define USART_BRR_DIV_F_MASK GENMASK(3, 0)
134#define USART_BRR_DIV_M_MASK GENMASK(15, 4)
135#define USART_BRR_DIV_M_SHIFT 4
136
137/* USART_CR1 */
138#define USART_CR1_SBK BIT(0)
139#define USART_CR1_RWU BIT(1) /* F4 */
140#define USART_CR1_UESM BIT(1) /* H7 */
117#define USART_CR1_RE BIT(2)
118#define USART_CR1_TE BIT(3)
119#define USART_CR1_IDLEIE BIT(4)
120#define USART_CR1_RXNEIE BIT(5)
121#define USART_CR1_TCIE BIT(6)
122#define USART_CR1_TXEIE BIT(7)
123#define USART_CR1_PEIE BIT(8)
124#define USART_CR1_PS BIT(9)

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171#define USART_CR3_CTSE BIT(9)
172#define USART_CR3_CTSIE BIT(10)
173#define USART_CR3_ONEBIT BIT(11)
174#define USART_CR3_OVRDIS BIT(12) /* F7 */
175#define USART_CR3_DDRE BIT(13) /* F7 */
176#define USART_CR3_DEM BIT(14) /* F7 */
177#define USART_CR3_DEP BIT(15) /* F7 */
178#define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */
141#define USART_CR1_RE BIT(2)
142#define USART_CR1_TE BIT(3)
143#define USART_CR1_IDLEIE BIT(4)
144#define USART_CR1_RXNEIE BIT(5)
145#define USART_CR1_TCIE BIT(6)
146#define USART_CR1_TXEIE BIT(7)
147#define USART_CR1_PEIE BIT(8)
148#define USART_CR1_PS BIT(9)

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195#define USART_CR3_CTSE BIT(9)
196#define USART_CR3_CTSIE BIT(10)
197#define USART_CR3_ONEBIT BIT(11)
198#define USART_CR3_OVRDIS BIT(12) /* F7 */
199#define USART_CR3_DDRE BIT(13) /* F7 */
200#define USART_CR3_DEM BIT(14) /* F7 */
201#define USART_CR3_DEP BIT(15) /* F7 */
202#define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */
203#define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */
204#define USART_CR3_WUS_START_BIT BIT(21) /* H7 */
205#define USART_CR3_WUFIE BIT(22) /* H7 */
179
180/* USART_GTPR */
181#define USART_GTPR_PSC_MASK GENMASK(7, 0)
182#define USART_GTPR_GT_MASK GENMASK(15, 8)
183
184/* USART_RTOR */
185#define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */
186#define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */

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199#define USART_ICR_ORECF BIT(3) /* F7 */
200#define USART_ICR_IDLECF BIT(4) /* F7 */
201#define USART_ICR_TCCF BIT(6) /* F7 */
202#define USART_ICR_LBDCF BIT(8) /* F7 */
203#define USART_ICR_CTSCF BIT(9) /* F7 */
204#define USART_ICR_RTOCF BIT(11) /* F7 */
205#define USART_ICR_EOBCF BIT(12) /* F7 */
206#define USART_ICR_CMCF BIT(17) /* F7 */
206
207/* USART_GTPR */
208#define USART_GTPR_PSC_MASK GENMASK(7, 0)
209#define USART_GTPR_GT_MASK GENMASK(15, 8)
210
211/* USART_RTOR */
212#define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */
213#define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */

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226#define USART_ICR_ORECF BIT(3) /* F7 */
227#define USART_ICR_IDLECF BIT(4) /* F7 */
228#define USART_ICR_TCCF BIT(6) /* F7 */
229#define USART_ICR_LBDCF BIT(8) /* F7 */
230#define USART_ICR_CTSCF BIT(9) /* F7 */
231#define USART_ICR_RTOCF BIT(11) /* F7 */
232#define USART_ICR_EOBCF BIT(12) /* F7 */
233#define USART_ICR_CMCF BIT(17) /* F7 */
234#define USART_ICR_WUCF BIT(20) /* H7 */
207
208#define STM32_SERIAL_NAME "ttyS"
209#define STM32_MAX_PORTS 8
210
211#define RX_BUF_L 200 /* dma rx buffer length */
212#define RX_BUF_P RX_BUF_L /* dma rx buffer period */
213#define TX_BUF_L 200 /* dma tx buffer length */
214

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220 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
221 unsigned char *rx_buf; /* dma rx buffer cpu address */
222 struct dma_chan *tx_ch; /* dma tx channel */
223 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
224 unsigned char *tx_buf; /* dma tx buffer cpu address */
225 int last_res;
226 bool tx_dma_busy; /* dma tx busy */
227 bool hw_flow_control;
235
236#define STM32_SERIAL_NAME "ttyS"
237#define STM32_MAX_PORTS 8
238
239#define RX_BUF_L 200 /* dma rx buffer length */
240#define RX_BUF_P RX_BUF_L /* dma rx buffer period */
241#define TX_BUF_L 200 /* dma tx buffer length */
242

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248 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
249 unsigned char *rx_buf; /* dma rx buffer cpu address */
250 struct dma_chan *tx_ch; /* dma tx channel */
251 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
252 unsigned char *tx_buf; /* dma tx buffer cpu address */
253 int last_res;
254 bool tx_dma_busy; /* dma tx busy */
255 bool hw_flow_control;
256 int wakeirq;
228};
229
230static struct stm32_port stm32_ports[STM32_MAX_PORTS];
231static struct uart_driver stm32_usart_driver;
257};
258
259static struct stm32_port stm32_ports[STM32_MAX_PORTS];
260static struct uart_driver stm32_usart_driver;