| stm32-usart.h (4c9f4865f4604744d4f1a43db22ac6ec9dc8e587) | stm32-usart.h (3db1d52466dc11dca4e47ef12a6e6e97f846af62) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald_baeza@yahoo.fr> 7 */ 8 --- 113 unchanged lines hidden (view full) --- 122#define USART_SR_CMF BIT(17) /* F7 */ 123#define USART_SR_SBKF BIT(18) /* F7 */ 124#define USART_SR_WUF BIT(20) /* H7 */ 125#define USART_SR_TEACK BIT(21) /* F7 */ 126#define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_FE | USART_SR_PE) 127/* Dummy bits */ 128#define USART_SR_DUMMY_RX BIT(16) 129 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald_baeza@yahoo.fr> 7 */ 8 --- 113 unchanged lines hidden (view full) --- 122#define USART_SR_CMF BIT(17) /* F7 */ 123#define USART_SR_SBKF BIT(18) /* F7 */ 124#define USART_SR_WUF BIT(20) /* H7 */ 125#define USART_SR_TEACK BIT(21) /* F7 */ 126#define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_FE | USART_SR_PE) 127/* Dummy bits */ 128#define USART_SR_DUMMY_RX BIT(16) 129 |
| 130/* USART_ICR (F7) */ 131#define USART_CR_TC BIT(6) 132 | |
| 133/* USART_DR */ 134#define USART_DR_MASK GENMASK(8, 0) 135 136/* USART_BRR */ 137#define USART_BRR_DIV_F_MASK GENMASK(3, 0) 138#define USART_BRR_DIV_M_MASK GENMASK(15, 4) 139#define USART_BRR_DIV_M_SHIFT 4 140#define USART_BRR_04_R_SHIFT 1 --- 141 unchanged lines hidden --- | 130/* USART_DR */ 131#define USART_DR_MASK GENMASK(8, 0) 132 133/* USART_BRR */ 134#define USART_BRR_DIV_F_MASK GENMASK(3, 0) 135#define USART_BRR_DIV_M_MASK GENMASK(15, 4) 136#define USART_BRR_DIV_M_SHIFT 4 137#define USART_BRR_04_R_SHIFT 1 --- 141 unchanged lines hidden --- |