stm32-usart.h (270e5a74fe4c78a857d65f1a129d3d77a36b8d58) stm32-usart.h (351a762aa8051960695a0f131731518e93b957fa)
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald_baeza@yahoo.fr>
6 * License terms: GNU General Public License (GPL), version 2
7 */
8

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21 u8 rdr;
22 u8 tdr;
23};
24
25struct stm32_usart_config {
26 u8 uart_enable_bit; /* USART_CR1_UE */
27 bool has_7bits_data;
28 bool has_wakeup;
1/*
2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald_baeza@yahoo.fr>
6 * License terms: GNU General Public License (GPL), version 2
7 */
8

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21 u8 rdr;
22 u8 tdr;
23};
24
25struct stm32_usart_config {
26 u8 uart_enable_bit; /* USART_CR1_UE */
27 bool has_7bits_data;
28 bool has_wakeup;
29 bool has_fifo;
29};
30
31struct stm32_usart_info {
32 struct stm32_usart_offsets ofs;
33 struct stm32_usart_config cfg;
34};
35
36#define UNDEF_REG 0xff

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89 .icr = 0x20,
90 .rdr = 0x24,
91 .tdr = 0x28,
92 },
93 .cfg = {
94 .uart_enable_bit = 0,
95 .has_7bits_data = true,
96 .has_wakeup = true,
30};
31
32struct stm32_usart_info {
33 struct stm32_usart_offsets ofs;
34 struct stm32_usart_config cfg;
35};
36
37#define UNDEF_REG 0xff

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90 .icr = 0x20,
91 .rdr = 0x24,
92 .tdr = 0x28,
93 },
94 .cfg = {
95 .uart_enable_bit = 0,
96 .has_7bits_data = true,
97 .has_wakeup = true,
98 .has_fifo = true,
97 }
98};
99
100/* USART_SR (F4) / USART_ISR (F7) */
101#define USART_SR_PE BIT(0)
102#define USART_SR_FE BIT(1)
103#define USART_SR_NF BIT(2)
104#define USART_SR_ORE BIT(3)

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154#define USART_CR1_CMIE BIT(14) /* F7 */
155#define USART_CR1_OVER8 BIT(15)
156#define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */
157#define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */
158#define USART_CR1_RTOIE BIT(26) /* F7 */
159#define USART_CR1_EOBIE BIT(27) /* F7 */
160#define USART_CR1_M1 BIT(28) /* F7 */
161#define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
99 }
100};
101
102/* USART_SR (F4) / USART_ISR (F7) */
103#define USART_SR_PE BIT(0)
104#define USART_SR_FE BIT(1)
105#define USART_SR_NF BIT(2)
106#define USART_SR_ORE BIT(3)

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156#define USART_CR1_CMIE BIT(14) /* F7 */
157#define USART_CR1_OVER8 BIT(15)
158#define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */
159#define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */
160#define USART_CR1_RTOIE BIT(26) /* F7 */
161#define USART_CR1_EOBIE BIT(27) /* F7 */
162#define USART_CR1_M1 BIT(28) /* F7 */
163#define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
164#define USART_CR1_FIFOEN BIT(29) /* H7 */
162
163/* USART_CR2 */
164#define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */
165#define USART_CR2_ADDM7 BIT(4) /* F7 */
166#define USART_CR2_LBDL BIT(5)
167#define USART_CR2_LBDIE BIT(6)
168#define USART_CR2_LBCL BIT(8)
169#define USART_CR2_CPHA BIT(9)

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248 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
249 unsigned char *rx_buf; /* dma rx buffer cpu address */
250 struct dma_chan *tx_ch; /* dma tx channel */
251 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
252 unsigned char *tx_buf; /* dma tx buffer cpu address */
253 int last_res;
254 bool tx_dma_busy; /* dma tx busy */
255 bool hw_flow_control;
165
166/* USART_CR2 */
167#define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */
168#define USART_CR2_ADDM7 BIT(4) /* F7 */
169#define USART_CR2_LBDL BIT(5)
170#define USART_CR2_LBDIE BIT(6)
171#define USART_CR2_LBCL BIT(8)
172#define USART_CR2_CPHA BIT(9)

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251 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
252 unsigned char *rx_buf; /* dma rx buffer cpu address */
253 struct dma_chan *tx_ch; /* dma tx channel */
254 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
255 unsigned char *tx_buf; /* dma tx buffer cpu address */
256 int last_res;
257 bool tx_dma_busy; /* dma tx busy */
258 bool hw_flow_control;
259 bool fifoen;
256 int wakeirq;
257};
258
259static struct stm32_port stm32_ports[STM32_MAX_PORTS];
260static struct uart_driver stm32_usart_driver;
260 int wakeirq;
261};
262
263static struct stm32_port stm32_ports[STM32_MAX_PORTS];
264static struct uart_driver stm32_usart_driver;