stm32-usart.c (f8bade6c9a6213c2c5ba6e5bf32415ecab6e41e5) stm32-usart.c (1631eeeaf084acdc29ca0370db8ea436692f71f5)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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209 return c;
210}
211
212static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
213{
214 struct tty_port *tport = &port->state->port;
215 struct stm32_port *stm32_port = to_stm32_port(port);
216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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209 return c;
210}
211
212static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
213{
214 struct tty_port *tport = &port->state->port;
215 struct stm32_port *stm32_port = to_stm32_port(port);
216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
217 unsigned long c;
217 unsigned long c, flags;
218 u32 sr;
219 char flag;
220
218 u32 sr;
219 char flag;
220
221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
222 pm_wakeup_event(tport->tty->dev, 0);
221 if (threaded)
222 spin_lock_irqsave(&port->lock, flags);
223 else
224 spin_lock(&port->lock);
223
224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
225 threaded)) {
226 sr |= USART_SR_DUMMY_RX;
227 flag = TTY_NORMAL;
228
229 /*
230 * Status bits has to be cleared before reading the RDR:

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271 }
272 }
273
274 if (uart_handle_sysrq_char(port, c))
275 continue;
276 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
277 }
278
225
226 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
227 threaded)) {
228 sr |= USART_SR_DUMMY_RX;
229 flag = TTY_NORMAL;
230
231 /*
232 * Status bits has to be cleared before reading the RDR:

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273 }
274 }
275
276 if (uart_handle_sysrq_char(port, c))
277 continue;
278 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
279 }
280
279 spin_unlock(&port->lock);
281 if (threaded)
282 spin_unlock_irqrestore(&port->lock, flags);
283 else
284 spin_unlock(&port->lock);
285
280 tty_flip_buffer_push(tport);
286 tty_flip_buffer_push(tport);
281 spin_lock(&port->lock);
282}
283
284static void stm32_usart_tx_dma_complete(void *arg)
285{
286 struct uart_port *port = arg;
287 struct stm32_port *stm32port = to_stm32_port(port);
288 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
287}
288
289static void stm32_usart_tx_dma_complete(void *arg)
290{
291 struct uart_port *port = arg;
292 struct stm32_port *stm32port = to_stm32_port(port);
293 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
294 unsigned long flags;
289
295
296 dmaengine_terminate_async(stm32port->tx_ch);
290 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
291 stm32port->tx_dma_busy = false;
292
293 /* Let's see if we have pending data to send */
297 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
298 stm32port->tx_dma_busy = false;
299
300 /* Let's see if we have pending data to send */
301 spin_lock_irqsave(&port->lock, flags);
294 stm32_usart_transmit_chars(port);
302 stm32_usart_transmit_chars(port);
303 spin_unlock_irqrestore(&port->lock, flags);
295}
296
297static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
298{
299 struct stm32_port *stm32_port = to_stm32_port(port);
300 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
301
302 /*

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450
451 if (uart_circ_empty(xmit))
452 stm32_usart_tx_interrupt_disable(port);
453}
454
455static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
456{
457 struct uart_port *port = ptr;
304}
305
306static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
307{
308 struct stm32_port *stm32_port = to_stm32_port(port);
309 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
310
311 /*

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459
460 if (uart_circ_empty(xmit))
461 stm32_usart_tx_interrupt_disable(port);
462}
463
464static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
465{
466 struct uart_port *port = ptr;
467 struct tty_port *tport = &port->state->port;
458 struct stm32_port *stm32_port = to_stm32_port(port);
459 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
460 u32 sr;
461
468 struct stm32_port *stm32_port = to_stm32_port(port);
469 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
470 u32 sr;
471
462 spin_lock(&port->lock);
463
464 sr = readl_relaxed(port->membase + ofs->isr);
465
466 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
467 writel_relaxed(USART_ICR_RTOCF,
468 port->membase + ofs->icr);
469
472 sr = readl_relaxed(port->membase + ofs->isr);
473
474 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
475 writel_relaxed(USART_ICR_RTOCF,
476 port->membase + ofs->icr);
477
470 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG)
478 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
479 /* Clear wake up flag and disable wake up interrupt */
471 writel_relaxed(USART_ICR_WUCF,
472 port->membase + ofs->icr);
480 writel_relaxed(USART_ICR_WUCF,
481 port->membase + ofs->icr);
482 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
483 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
484 pm_wakeup_event(tport->tty->dev, 0);
485 }
473
474 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
475 stm32_usart_receive_chars(port, false);
476
486
487 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
488 stm32_usart_receive_chars(port, false);
489
477 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
490 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
491 spin_lock(&port->lock);
478 stm32_usart_transmit_chars(port);
492 stm32_usart_transmit_chars(port);
493 spin_unlock(&port->lock);
494 }
479
495
480 spin_unlock(&port->lock);
481
482 if (stm32_port->rx_ch)
483 return IRQ_WAKE_THREAD;
484 else
485 return IRQ_HANDLED;
486}
487
488static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
489{
490 struct uart_port *port = ptr;
491 struct stm32_port *stm32_port = to_stm32_port(port);
492
496 if (stm32_port->rx_ch)
497 return IRQ_WAKE_THREAD;
498 else
499 return IRQ_HANDLED;
500}
501
502static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
503{
504 struct uart_port *port = ptr;
505 struct stm32_port *stm32_port = to_stm32_port(port);
506
493 spin_lock(&port->lock);
494
495 if (stm32_port->rx_ch)
496 stm32_usart_receive_chars(port, true);
497
507 if (stm32_port->rx_ch)
508 stm32_usart_receive_chars(port, true);
509
498 spin_unlock(&port->lock);
499
500 return IRQ_HANDLED;
501}
502
503static unsigned int stm32_usart_tx_empty(struct uart_port *port)
504{
505 struct stm32_port *stm32_port = to_stm32_port(port);
506 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
507
510 return IRQ_HANDLED;
511}
512
513static unsigned int stm32_usart_tx_empty(struct uart_port *port)
514{
515 struct stm32_port *stm32_port = to_stm32_port(port);
516 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
517
508 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
518 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
519 return TIOCSER_TEMT;
520
521 return 0;
509}
510
511static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
512{
513 struct stm32_port *stm32_port = to_stm32_port(port);
514 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
515
516 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))

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579 mctrl_gpio_set(stm32_port->gpios,
580 stm32_port->port.mctrl & ~TIOCM_RTS);
581 }
582 }
583
584 stm32_usart_transmit_chars(port);
585}
586
522}
523
524static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
525{
526 struct stm32_port *stm32_port = to_stm32_port(port);
527 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
528
529 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))

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592 mctrl_gpio_set(stm32_port->gpios,
593 stm32_port->port.mctrl & ~TIOCM_RTS);
594 }
595 }
596
597 stm32_usart_transmit_chars(port);
598}
599
600/* Flush the transmit buffer. */
601static void stm32_usart_flush_buffer(struct uart_port *port)
602{
603 struct stm32_port *stm32_port = to_stm32_port(port);
604 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
605
606 if (stm32_port->tx_ch) {
607 dmaengine_terminate_async(stm32_port->tx_ch);
608 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
609 stm32_port->tx_dma_busy = false;
610 }
611}
612
587/* Throttle the remote when input buffer is about to overflow. */
588static void stm32_usart_throttle(struct uart_port *port)
589{
590 struct stm32_port *stm32_port = to_stm32_port(port);
591 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
592 unsigned long flags;
593
594 spin_lock_irqsave(&port->lock, flags);

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629static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
630{
631}
632
633static int stm32_usart_startup(struct uart_port *port)
634{
635 struct stm32_port *stm32_port = to_stm32_port(port);
636 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
613/* Throttle the remote when input buffer is about to overflow. */
614static void stm32_usart_throttle(struct uart_port *port)
615{
616 struct stm32_port *stm32_port = to_stm32_port(port);
617 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
618 unsigned long flags;
619
620 spin_lock_irqsave(&port->lock, flags);

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655static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
656{
657}
658
659static int stm32_usart_startup(struct uart_port *port)
660{
661 struct stm32_port *stm32_port = to_stm32_port(port);
662 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
663 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
637 const char *name = to_platform_device(port->dev)->name;
638 u32 val;
639 int ret;
640
641 ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
642 stm32_usart_threaded_interrupt,
643 IRQF_NO_SUSPEND, name, port);
644 if (ret)
645 return ret;
646
647 /* RX FIFO Flush */
648 if (ofs->rqr != UNDEF_REG)
664 const char *name = to_platform_device(port->dev)->name;
665 u32 val;
666 int ret;
667
668 ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
669 stm32_usart_threaded_interrupt,
670 IRQF_NO_SUSPEND, name, port);
671 if (ret)
672 return ret;
673
674 /* RX FIFO Flush */
675 if (ofs->rqr != UNDEF_REG)
649 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
676 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
650
677
651 /* Tx and RX FIFO configuration */
652 if (stm32_port->fifoen) {
653 val = readl_relaxed(port->membase + ofs->cr3);
654 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
655 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
656 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
657 writel_relaxed(val, port->membase + ofs->cr3);
658 }
659
660 /* RX FIFO enabling */
661 val = stm32_port->cr1_irq | USART_CR1_RE;
662 if (stm32_port->fifoen)
663 val |= USART_CR1_FIFOEN;
678 /* RX enabling */
679 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
664 stm32_usart_set_bits(port, ofs->cr1, val);
665
666 return 0;
667}
668
669static void stm32_usart_shutdown(struct uart_port *port)
670{
671 struct stm32_port *stm32_port = to_stm32_port(port);

--- 14 unchanged lines hidden (view full) ---

686 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
687 isr, (isr & USART_SR_TC),
688 10, 100000);
689
690 /* Send the TC error message only when ISR_TC is not set */
691 if (ret)
692 dev_err(port->dev, "Transmission is not complete\n");
693
680 stm32_usart_set_bits(port, ofs->cr1, val);
681
682 return 0;
683}
684
685static void stm32_usart_shutdown(struct uart_port *port)
686{
687 struct stm32_port *stm32_port = to_stm32_port(port);

--- 14 unchanged lines hidden (view full) ---

702 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
703 isr, (isr & USART_SR_TC),
704 10, 100000);
705
706 /* Send the TC error message only when ISR_TC is not set */
707 if (ret)
708 dev_err(port->dev, "Transmission is not complete\n");
709
710 /* flush RX & TX FIFO */
711 if (ofs->rqr != UNDEF_REG)
712 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
713 port->membase + ofs->rqr);
714
694 stm32_usart_clr_bits(port, ofs->cr1, val);
695
696 free_irq(port->irq, port);
697}
698
699static unsigned int stm32_usart_get_databits(struct ktermios *termios)
700{
701 unsigned int bits;

--- 30 unchanged lines hidden (view full) ---

732{
733 struct stm32_port *stm32_port = to_stm32_port(port);
734 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
735 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
736 struct serial_rs485 *rs485conf = &port->rs485;
737 unsigned int baud, bits;
738 u32 usartdiv, mantissa, fraction, oversampling;
739 tcflag_t cflag = termios->c_cflag;
715 stm32_usart_clr_bits(port, ofs->cr1, val);
716
717 free_irq(port->irq, port);
718}
719
720static unsigned int stm32_usart_get_databits(struct ktermios *termios)
721{
722 unsigned int bits;

--- 30 unchanged lines hidden (view full) ---

753{
754 struct stm32_port *stm32_port = to_stm32_port(port);
755 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
756 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
757 struct serial_rs485 *rs485conf = &port->rs485;
758 unsigned int baud, bits;
759 u32 usartdiv, mantissa, fraction, oversampling;
760 tcflag_t cflag = termios->c_cflag;
740 u32 cr1, cr2, cr3;
761 u32 cr1, cr2, cr3, isr;
741 unsigned long flags;
762 unsigned long flags;
763 int ret;
742
743 if (!stm32_port->hw_flow_control)
744 cflag &= ~CRTSCTS;
745
746 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
747
748 spin_lock_irqsave(&port->lock, flags);
749
764
765 if (!stm32_port->hw_flow_control)
766 cflag &= ~CRTSCTS;
767
768 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
769
770 spin_lock_irqsave(&port->lock, flags);
771
772 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
773 isr,
774 (isr & USART_SR_TC),
775 10, 100000);
776
777 /* Send the TC error message only when ISR_TC is not set. */
778 if (ret)
779 dev_err(port->dev, "Transmission is not complete\n");
780
750 /* Stop serial port and reset value */
751 writel_relaxed(0, port->membase + ofs->cr1);
752
753 /* flush RX & TX FIFO */
754 if (ofs->rqr != UNDEF_REG)
781 /* Stop serial port and reset value */
782 writel_relaxed(0, port->membase + ofs->cr1);
783
784 /* flush RX & TX FIFO */
785 if (ofs->rqr != UNDEF_REG)
755 stm32_usart_set_bits(port, ofs->rqr,
756 USART_RQR_TXFRQ | USART_RQR_RXFRQ);
786 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
787 port->membase + ofs->rqr);
757
758 cr1 = USART_CR1_TE | USART_CR1_RE;
759 if (stm32_port->fifoen)
760 cr1 |= USART_CR1_FIFOEN;
761 cr2 = 0;
788
789 cr1 = USART_CR1_TE | USART_CR1_RE;
790 if (stm32_port->fifoen)
791 cr1 |= USART_CR1_FIFOEN;
792 cr2 = 0;
793
794 /* Tx and RX FIFO configuration */
762 cr3 = readl_relaxed(port->membase + ofs->cr3);
795 cr3 = readl_relaxed(port->membase + ofs->cr3);
763 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
764 | USART_CR3_TXFTCFG_MASK;
796 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
797 if (stm32_port->fifoen) {
798 cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
799 cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
800 cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
801 }
765
766 if (cflag & CSTOPB)
767 cr2 |= USART_CR2_STOP_2B;
768
769 bits = stm32_usart_get_databits(termios);
770 stm32_port->rdr_mask = (BIT(bits) - 1);
771
772 if (cflag & PARENB) {

--- 39 unchanged lines hidden (view full) ---

812 cr1 |= USART_CR1_PS;
813
814 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
815 if (cflag & CRTSCTS) {
816 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
817 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
818 }
819
802
803 if (cflag & CSTOPB)
804 cr2 |= USART_CR2_STOP_2B;
805
806 bits = stm32_usart_get_databits(termios);
807 stm32_port->rdr_mask = (BIT(bits) - 1);
808
809 if (cflag & PARENB) {

--- 39 unchanged lines hidden (view full) ---

849 cr1 |= USART_CR1_PS;
850
851 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
852 if (cflag & CRTSCTS) {
853 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
854 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
855 }
856
820 /* Handle modem control interrupts */
821 if (UART_ENABLE_MS(port, termios->c_cflag))
822 stm32_usart_enable_ms(port);
823 else
824 stm32_usart_disable_ms(port);
825
826 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
827
828 /*
829 * The USART supports 16 or 8 times oversampling.
830 * By default we prefer 16 times oversampling, so that the receiver
831 * has a better tolerance to clock deviations.
832 * 8 times oversampling is only used to achieve higher speeds.
833 */

--- 53 unchanged lines hidden (view full) ---

887 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
888 }
889
890 } else {
891 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
892 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
893 }
894
857 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
858
859 /*
860 * The USART supports 16 or 8 times oversampling.
861 * By default we prefer 16 times oversampling, so that the receiver
862 * has a better tolerance to clock deviations.
863 * 8 times oversampling is only used to achieve higher speeds.
864 */

--- 53 unchanged lines hidden (view full) ---

918 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
919 }
920
921 } else {
922 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
923 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
924 }
925
926 /* Configure wake up from low power on start bit detection */
927 if (stm32_port->wakeirq > 0) {
928 cr3 &= ~USART_CR3_WUS_MASK;
929 cr3 |= USART_CR3_WUS_START_BIT;
930 }
931
895 writel_relaxed(cr3, port->membase + ofs->cr3);
896 writel_relaxed(cr2, port->membase + ofs->cr2);
897 writel_relaxed(cr1, port->membase + ofs->cr1);
898
899 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
900 spin_unlock_irqrestore(&port->lock, flags);
932 writel_relaxed(cr3, port->membase + ofs->cr3);
933 writel_relaxed(cr2, port->membase + ofs->cr2);
934 writel_relaxed(cr1, port->membase + ofs->cr1);
935
936 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
937 spin_unlock_irqrestore(&port->lock, flags);
938
939 /* Handle modem control interrupts */
940 if (UART_ENABLE_MS(port, termios->c_cflag))
941 stm32_usart_enable_ms(port);
942 else
943 stm32_usart_disable_ms(port);
901}
902
903static const char *stm32_usart_type(struct uart_port *port)
904{
905 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
906}
907
908static void stm32_usart_release_port(struct uart_port *port)

--- 48 unchanged lines hidden (view full) ---

957 .start_tx = stm32_usart_start_tx,
958 .throttle = stm32_usart_throttle,
959 .unthrottle = stm32_usart_unthrottle,
960 .stop_rx = stm32_usart_stop_rx,
961 .enable_ms = stm32_usart_enable_ms,
962 .break_ctl = stm32_usart_break_ctl,
963 .startup = stm32_usart_startup,
964 .shutdown = stm32_usart_shutdown,
944}
945
946static const char *stm32_usart_type(struct uart_port *port)
947{
948 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
949}
950
951static void stm32_usart_release_port(struct uart_port *port)

--- 48 unchanged lines hidden (view full) ---

1000 .start_tx = stm32_usart_start_tx,
1001 .throttle = stm32_usart_throttle,
1002 .unthrottle = stm32_usart_unthrottle,
1003 .stop_rx = stm32_usart_stop_rx,
1004 .enable_ms = stm32_usart_enable_ms,
1005 .break_ctl = stm32_usart_break_ctl,
1006 .startup = stm32_usart_startup,
1007 .shutdown = stm32_usart_shutdown,
1008 .flush_buffer = stm32_usart_flush_buffer,
965 .set_termios = stm32_usart_set_termios,
966 .pm = stm32_usart_pm,
967 .type = stm32_usart_type,
968 .release_port = stm32_usart_release_port,
969 .request_port = stm32_usart_request_port,
970 .config_port = stm32_usart_config_port,
971 .verify_port = stm32_usart_verify_port,
972};

--- 274 unchanged lines hidden (view full) ---

1247 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1248 stm32port->wakeirq);
1249 if (ret)
1250 goto err_nowup;
1251
1252 device_set_wakeup_enable(&pdev->dev, false);
1253 }
1254
1009 .set_termios = stm32_usart_set_termios,
1010 .pm = stm32_usart_pm,
1011 .type = stm32_usart_type,
1012 .release_port = stm32_usart_release_port,
1013 .request_port = stm32_usart_request_port,
1014 .config_port = stm32_usart_config_port,
1015 .verify_port = stm32_usart_verify_port,
1016};

--- 274 unchanged lines hidden (view full) ---

1291 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1292 stm32port->wakeirq);
1293 if (ret)
1294 goto err_nowup;
1295
1296 device_set_wakeup_enable(&pdev->dev, false);
1297 }
1298
1255 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1256 if (ret)
1257 goto err_wirq;
1258
1259 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
1260 if (ret)
1261 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1262
1263 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
1264 if (ret)
1265 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1266
1267 platform_set_drvdata(pdev, &stm32port->port);
1268
1269 pm_runtime_get_noresume(&pdev->dev);
1270 pm_runtime_set_active(&pdev->dev);
1271 pm_runtime_enable(&pdev->dev);
1299 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
1300 if (ret)
1301 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1302
1303 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
1304 if (ret)
1305 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1306
1307 platform_set_drvdata(pdev, &stm32port->port);
1308
1309 pm_runtime_get_noresume(&pdev->dev);
1310 pm_runtime_set_active(&pdev->dev);
1311 pm_runtime_enable(&pdev->dev);
1312
1313 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1314 if (ret)
1315 goto err_port;
1316
1272 pm_runtime_put_sync(&pdev->dev);
1273
1274 return 0;
1275
1317 pm_runtime_put_sync(&pdev->dev);
1318
1319 return 0;
1320
1276err_wirq:
1321err_port:
1322 pm_runtime_disable(&pdev->dev);
1323 pm_runtime_set_suspended(&pdev->dev);
1324 pm_runtime_put_noidle(&pdev->dev);
1325
1326 if (stm32port->rx_ch) {
1327 dmaengine_terminate_async(stm32port->rx_ch);
1328 dma_release_channel(stm32port->rx_ch);
1329 }
1330
1331 if (stm32port->rx_dma_buf)
1332 dma_free_coherent(&pdev->dev,
1333 RX_BUF_L, stm32port->rx_buf,
1334 stm32port->rx_dma_buf);
1335
1336 if (stm32port->tx_ch) {
1337 dmaengine_terminate_async(stm32port->tx_ch);
1338 dma_release_channel(stm32port->tx_ch);
1339 }
1340
1341 if (stm32port->tx_dma_buf)
1342 dma_free_coherent(&pdev->dev,
1343 TX_BUF_L, stm32port->tx_buf,
1344 stm32port->tx_dma_buf);
1345
1277 if (stm32port->wakeirq > 0)
1278 dev_pm_clear_wake_irq(&pdev->dev);
1279
1280err_nowup:
1281 if (stm32port->wakeirq > 0)
1282 device_init_wakeup(&pdev->dev, false);
1283
1284err_uninit:

--- 5 unchanged lines hidden (view full) ---

1290static int stm32_usart_serial_remove(struct platform_device *pdev)
1291{
1292 struct uart_port *port = platform_get_drvdata(pdev);
1293 struct stm32_port *stm32_port = to_stm32_port(port);
1294 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1295 int err;
1296
1297 pm_runtime_get_sync(&pdev->dev);
1346 if (stm32port->wakeirq > 0)
1347 dev_pm_clear_wake_irq(&pdev->dev);
1348
1349err_nowup:
1350 if (stm32port->wakeirq > 0)
1351 device_init_wakeup(&pdev->dev, false);
1352
1353err_uninit:

--- 5 unchanged lines hidden (view full) ---

1359static int stm32_usart_serial_remove(struct platform_device *pdev)
1360{
1361 struct uart_port *port = platform_get_drvdata(pdev);
1362 struct stm32_port *stm32_port = to_stm32_port(port);
1363 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1364 int err;
1365
1366 pm_runtime_get_sync(&pdev->dev);
1367 err = uart_remove_one_port(&stm32_usart_driver, port);
1368 if (err)
1369 return(err);
1298
1370
1371 pm_runtime_disable(&pdev->dev);
1372 pm_runtime_set_suspended(&pdev->dev);
1373 pm_runtime_put_noidle(&pdev->dev);
1374
1299 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1300
1375 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1376
1301 if (stm32_port->rx_ch)
1377 if (stm32_port->rx_ch) {
1378 dmaengine_terminate_async(stm32_port->rx_ch);
1302 dma_release_channel(stm32_port->rx_ch);
1379 dma_release_channel(stm32_port->rx_ch);
1380 }
1303
1304 if (stm32_port->rx_dma_buf)
1305 dma_free_coherent(&pdev->dev,
1306 RX_BUF_L, stm32_port->rx_buf,
1307 stm32_port->rx_dma_buf);
1308
1309 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1310
1381
1382 if (stm32_port->rx_dma_buf)
1383 dma_free_coherent(&pdev->dev,
1384 RX_BUF_L, stm32_port->rx_buf,
1385 stm32_port->rx_dma_buf);
1386
1387 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1388
1311 if (stm32_port->tx_ch)
1389 if (stm32_port->tx_ch) {
1390 dmaengine_terminate_async(stm32_port->tx_ch);
1312 dma_release_channel(stm32_port->tx_ch);
1391 dma_release_channel(stm32_port->tx_ch);
1392 }
1313
1314 if (stm32_port->tx_dma_buf)
1315 dma_free_coherent(&pdev->dev,
1316 TX_BUF_L, stm32_port->tx_buf,
1317 stm32_port->tx_dma_buf);
1318
1319 if (stm32_port->wakeirq > 0) {
1320 dev_pm_clear_wake_irq(&pdev->dev);
1321 device_init_wakeup(&pdev->dev, false);
1322 }
1323
1324 stm32_usart_deinit_port(stm32_port);
1325
1393
1394 if (stm32_port->tx_dma_buf)
1395 dma_free_coherent(&pdev->dev,
1396 TX_BUF_L, stm32_port->tx_buf,
1397 stm32_port->tx_dma_buf);
1398
1399 if (stm32_port->wakeirq > 0) {
1400 dev_pm_clear_wake_irq(&pdev->dev);
1401 device_init_wakeup(&pdev->dev, false);
1402 }
1403
1404 stm32_usart_deinit_port(stm32_port);
1405
1326 err = uart_remove_one_port(&stm32_usart_driver, port);
1327
1328 pm_runtime_disable(&pdev->dev);
1329 pm_runtime_put_noidle(&pdev->dev);
1330
1331 return err;
1406 return 0;
1332}
1333
1334#ifdef CONFIG_SERIAL_STM32_CONSOLE
1335static void stm32_usart_console_putchar(struct uart_port *port, int ch)
1336{
1337 struct stm32_port *stm32_port = to_stm32_port(port);
1338 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1339

--- 91 unchanged lines hidden (view full) ---

1431 .cons = STM32_SERIAL_CONSOLE,
1432};
1433
1434static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1435 bool enable)
1436{
1437 struct stm32_port *stm32_port = to_stm32_port(port);
1438 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1407}
1408
1409#ifdef CONFIG_SERIAL_STM32_CONSOLE
1410static void stm32_usart_console_putchar(struct uart_port *port, int ch)
1411{
1412 struct stm32_port *stm32_port = to_stm32_port(port);
1413 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1414

--- 91 unchanged lines hidden (view full) ---

1506 .cons = STM32_SERIAL_CONSOLE,
1507};
1508
1509static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1510 bool enable)
1511{
1512 struct stm32_port *stm32_port = to_stm32_port(port);
1513 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1439 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1440 u32 val;
1441
1442 if (stm32_port->wakeirq <= 0)
1443 return;
1444
1514
1515 if (stm32_port->wakeirq <= 0)
1516 return;
1517
1518 /*
1519 * Enable low-power wake-up and wake-up irq if argument is set to
1520 * "enable", disable low-power wake-up and wake-up irq otherwise
1521 */
1445 if (enable) {
1522 if (enable) {
1446 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1447 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1523 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1448 val = readl_relaxed(port->membase + ofs->cr3);
1449 val &= ~USART_CR3_WUS_MASK;
1450 /* Enable Wake up interrupt from low power on start bit */
1451 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1452 writel_relaxed(val, port->membase + ofs->cr3);
1453 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1524 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
1454 } else {
1455 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1525 } else {
1526 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1527 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
1456 }
1457}
1458
1459static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
1460{
1461 struct uart_port *port = dev_get_drvdata(dev);
1462
1463 uart_suspend_port(&stm32_usart_driver, port);
1464
1528 }
1529}
1530
1531static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
1532{
1533 struct uart_port *port = dev_get_drvdata(dev);
1534
1535 uart_suspend_port(&stm32_usart_driver, port);
1536
1465 if (device_may_wakeup(dev))
1537 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1466 stm32_usart_serial_en_wakeup(port, true);
1467 else
1468 stm32_usart_serial_en_wakeup(port, false);
1469
1470 /*
1471 * When "no_console_suspend" is enabled, keep the pinctrl default state
1472 * and rely on bootloader stage to restore this state upon resume.
1473 * Otherwise, apply the idle or sleep states depending on wakeup
1474 * capabilities.
1475 */
1476 if (console_suspend_enabled || !uart_console(port)) {
1538 stm32_usart_serial_en_wakeup(port, true);
1539 else
1540 stm32_usart_serial_en_wakeup(port, false);
1541
1542 /*
1543 * When "no_console_suspend" is enabled, keep the pinctrl default state
1544 * and rely on bootloader stage to restore this state upon resume.
1545 * Otherwise, apply the idle or sleep states depending on wakeup
1546 * capabilities.
1547 */
1548 if (console_suspend_enabled || !uart_console(port)) {
1477 if (device_may_wakeup(dev))
1549 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1478 pinctrl_pm_select_idle_state(dev);
1479 else
1480 pinctrl_pm_select_sleep_state(dev);
1481 }
1482
1483 return 0;
1484}
1485
1486static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
1487{
1488 struct uart_port *port = dev_get_drvdata(dev);
1489
1490 pinctrl_pm_select_default_state(dev);
1491
1550 pinctrl_pm_select_idle_state(dev);
1551 else
1552 pinctrl_pm_select_sleep_state(dev);
1553 }
1554
1555 return 0;
1556}
1557
1558static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
1559{
1560 struct uart_port *port = dev_get_drvdata(dev);
1561
1562 pinctrl_pm_select_default_state(dev);
1563
1492 if (device_may_wakeup(dev))
1564 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1493 stm32_usart_serial_en_wakeup(port, false);
1494
1495 return uart_resume_port(&stm32_usart_driver, port);
1496}
1497
1498static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1499{
1500 struct uart_port *port = dev_get_drvdata(dev);

--- 64 unchanged lines hidden --- 		1565 stm32_usart_serial_en_wakeup(port, false);
1566
1567 return uart_resume_port(&stm32_usart_driver, port);
1568}
1569
1570static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1571{
1572 struct uart_port *port = dev_get_drvdata(dev);

--- 64 unchanged lines hidden ---