stm32-usart.c (e359b4411c2836cf87c8776682d1b594635570de) stm32-usart.c (cea37afd28f1bb7ca09a0c27e75f89cf2df9147d)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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265 } else if (sr & USART_SR_FE) {
266 if (!c)
267 flag = TTY_BREAK;
268 else
269 flag = TTY_FRAME;
270 }
271 }
272
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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265 } else if (sr & USART_SR_FE) {
266 if (!c)
267 flag = TTY_BREAK;
268 else
269 flag = TTY_FRAME;
270 }
271 }
272
273 if (uart_handle_sysrq_char(port, c))
273 if (uart_prepare_sysrq_char(port, c))
274 continue;
275 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
276 }
277
274 continue;
275 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
276 }
277
278 spin_unlock(&port->lock);
278 uart_unlock_and_check_sysrq(port);
279
280 tty_flip_buffer_push(tport);
281}
282
283static void stm32_usart_tx_dma_complete(void *arg)
284{
285 struct uart_port *port = arg;
286 struct stm32_port *stm32port = to_stm32_port(port);

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1425 struct uart_port *port = &stm32_ports[co->index].port;
1426 struct stm32_port *stm32_port = to_stm32_port(port);
1427 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1428 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1429 unsigned long flags;
1430 u32 old_cr1, new_cr1;
1431 int locked = 1;
1432
279
280 tty_flip_buffer_push(tport);
281}
282
283static void stm32_usart_tx_dma_complete(void *arg)
284{
285 struct uart_port *port = arg;
286 struct stm32_port *stm32port = to_stm32_port(port);

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1425 struct uart_port *port = &stm32_ports[co->index].port;
1426 struct stm32_port *stm32_port = to_stm32_port(port);
1427 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1428 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1429 unsigned long flags;
1430 u32 old_cr1, new_cr1;
1431 int locked = 1;
1432
1433 local_irq_save(flags);
1434 if (port->sysrq)
1435 locked = 0;
1436 else if (oops_in_progress)
1437 locked = spin_trylock(&port->lock);
1433 if (oops_in_progress)
1434 locked = spin_trylock_irqsave(&port->lock, flags);
1438 else
1435 else
1439 spin_lock(&port->lock);
1436 spin_lock_irqsave(&port->lock, flags);
1440
1441 /* Save and disable interrupts, enable the transmitter */
1442 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1443 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1444 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1445 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1446
1447 uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1448
1449 /* Restore interrupt state */
1450 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1451
1452 if (locked)
1437
1438 /* Save and disable interrupts, enable the transmitter */
1439 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1440 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1441 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1442 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1443
1444 uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1445
1446 /* Restore interrupt state */
1447 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1448
1449 if (locked)
1453 spin_unlock(&port->lock);
1454 local_irq_restore(flags);
1450 spin_unlock_irqrestore(&port->lock, flags);
1455}
1456
1457static int stm32_usart_console_setup(struct console *co, char *options)
1458{
1459 struct stm32_port *stm32port;
1460 int baud = 9600;
1461 int bits = 8;
1462 int parity = 'n';

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1452
1453static int stm32_usart_console_setup(struct console *co, char *options)
1454{
1455 struct stm32_port *stm32port;
1456 int baud = 9600;
1457 int bits = 8;
1458 int parity = 'n';

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