stm32-usart.c (db89728abad5ab6b8f30349142897bd55f1f5b00) stm32-usart.c (00bc5e8fc91743753a3ac9de1e9567e844ae3967)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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505 */
506 return stm32_port->tx_dma_busy;
507}
508
509static void stm32_usart_tx_dma_complete(void *arg)
510{
511 struct uart_port *port = arg;
512 struct stm32_port *stm32port = to_stm32_port(port);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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505 */
506 return stm32_port->tx_dma_busy;
507}
508
509static void stm32_usart_tx_dma_complete(void *arg)
510{
511 struct uart_port *port = arg;
512 struct stm32_port *stm32port = to_stm32_port(port);
513 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
514 unsigned long flags;
515
513 unsigned long flags;
514
516 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
517 stm32_usart_tx_dma_terminate(stm32port);
518
519 /* Let's see if we have pending data to send */
520 spin_lock_irqsave(&port->lock, flags);
521 stm32_usart_transmit_chars(port);
522 spin_unlock_irqrestore(&port->lock, flags);
523}
524

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597 stm32_usart_tx_interrupt_disable(port);
598 else
599 stm32_usart_tx_interrupt_enable(port);
600}
601
602static void stm32_usart_transmit_chars_dma(struct uart_port *port)
603{
604 struct stm32_port *stm32port = to_stm32_port(port);
515 stm32_usart_tx_dma_terminate(stm32port);
516
517 /* Let's see if we have pending data to send */
518 spin_lock_irqsave(&port->lock, flags);
519 stm32_usart_transmit_chars(port);
520 spin_unlock_irqrestore(&port->lock, flags);
521}
522

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595 stm32_usart_tx_interrupt_disable(port);
596 else
597 stm32_usart_tx_interrupt_enable(port);
598}
599
600static void stm32_usart_transmit_chars_dma(struct uart_port *port)
601{
602 struct stm32_port *stm32port = to_stm32_port(port);
605 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
606 struct circ_buf *xmit = &port->state->xmit;
607 struct dma_async_tx_descriptor *desc = NULL;
608 unsigned int count;
609 int ret;
610
611 if (stm32_usart_tx_dma_started(stm32port)) {
612 if (dmaengine_tx_status(stm32port->tx_ch,
613 stm32port->tx_ch->cookie,

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662 /* Push current DMA TX transaction in the pending queue */
663 /* DMA no yet started, safe to free resources */
664 if (dma_submit_error(dmaengine_submit(desc)))
665 goto dma_err;
666
667 /* Issue pending DMA TX requests */
668 dma_async_issue_pending(stm32port->tx_ch);
669
603 struct circ_buf *xmit = &port->state->xmit;
604 struct dma_async_tx_descriptor *desc = NULL;
605 unsigned int count;
606 int ret;
607
608 if (stm32_usart_tx_dma_started(stm32port)) {
609 if (dmaengine_tx_status(stm32port->tx_ch,
610 stm32port->tx_ch->cookie,

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659 /* Push current DMA TX transaction in the pending queue */
660 /* DMA no yet started, safe to free resources */
661 if (dma_submit_error(dmaengine_submit(desc)))
662 goto dma_err;
663
664 /* Issue pending DMA TX requests */
665 dma_async_issue_pending(stm32port->tx_ch);
666
670 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
671
672 uart_xmit_advance(port, count);
673
674 return;
675
676dma_err:
677 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
678 stm32_usart_tx_dma_terminate(stm32port);
679

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1265 * This also enables break reception when using DMA.
1266 */
1267 cr1 |= USART_CR1_PEIE;
1268 cr3 |= USART_CR3_EIE;
1269 cr3 |= USART_CR3_DMAR;
1270 cr3 |= USART_CR3_DDRE;
1271 }
1272
667 uart_xmit_advance(port, count);
668
669 return;
670
671dma_err:
672 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
673 stm32_usart_tx_dma_terminate(stm32port);
674

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1260 * This also enables break reception when using DMA.
1261 */
1262 cr1 |= USART_CR1_PEIE;
1263 cr3 |= USART_CR3_EIE;
1264 cr3 |= USART_CR3_DMAR;
1265 cr3 |= USART_CR3_DDRE;
1266 }
1267
1268 if (stm32_port->tx_ch)
1269 cr3 |= USART_CR3_DMAT;
1270
1273 if (rs485conf->flags & SER_RS485_ENABLED) {
1274 stm32_usart_config_reg_rs485(&cr1, &cr3,
1275 rs485conf->delay_rts_before_send,
1276 rs485conf->delay_rts_after_send,
1277 baud);
1278 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
1279 cr3 &= ~USART_CR3_DEP;
1280 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;

--- 846 unchanged lines hidden --- 		1271 if (rs485conf->flags & SER_RS485_ENABLED) {
1272 stm32_usart_config_reg_rs485(&cr1, &cr3,
1273 rs485conf->delay_rts_before_send,
1274 rs485conf->delay_rts_after_send,
1275 baud);
1276 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
1277 cr3 &= ~USART_CR3_DEP;
1278 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;

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