stm32-usart.c (d825f0bea20f49a8f413a6acd7c4100ea55edf6d) stm32-usart.c (e0f2a902c9f02fcb36c22f63e0db67e73375c843)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@st.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)
9 */
10
11#include <linux/clk.h>
12#include <linux/console.h>
13#include <linux/delay.h>
14#include <linux/dma-direction.h>

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29#include <linux/spinlock.h>
30#include <linux/sysrq.h>
31#include <linux/tty_flip.h>
32#include <linux/tty.h>
33
34#include "serial_mctrl_gpio.h"
35#include "stm32-usart.h"
36
8 *
9 * Inspired by st-asc.c from STMicroelectronics (c)
10 */
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/dma-direction.h>

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30#include <linux/spinlock.h>
31#include <linux/sysrq.h>
32#include <linux/tty_flip.h>
33#include <linux/tty.h>
34
35#include "serial_mctrl_gpio.h"
36#include "stm32-usart.h"
37
37static void stm32_stop_tx(struct uart_port *port);
38static void stm32_transmit_chars(struct uart_port *port);
38static void stm32_usart_stop_tx(struct uart_port *port);
39static void stm32_usart_transmit_chars(struct uart_port *port);
39
40static inline struct stm32_port *to_stm32_port(struct uart_port *port)
41{
42 return container_of(port, struct stm32_port, port);
43}
44
40
41static inline struct stm32_port *to_stm32_port(struct uart_port *port)
42{
43 return container_of(port, struct stm32_port, port);
44}
45
45static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
46static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
46{
47 u32 val;
48
49 val = readl_relaxed(port->membase + reg);
50 val |= bits;
51 writel_relaxed(val, port->membase + reg);
52}
53
47{
48 u32 val;
49
50 val = readl_relaxed(port->membase + reg);
51 val |= bits;
52 writel_relaxed(val, port->membase + reg);
53}
54
54static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
55static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
55{
56 u32 val;
57
58 val = readl_relaxed(port->membase + reg);
59 val &= ~bits;
60 writel_relaxed(val, port->membase + reg);
61}
62
56{
57 u32 val;
58
59 val = readl_relaxed(port->membase + reg);
60 val &= ~bits;
61 writel_relaxed(val, port->membase + reg);
62}
63
63static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
64 u32 delay_DDE, u32 baud)
64static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
65 u32 delay_DDE, u32 baud)
65{
66 u32 rs485_deat_dedt;
67 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
68 bool over8;
69
70 *cr3 |= USART_CR3_DEM;
71 over8 = *cr1 & USART_CR1_OVER8;
72

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90 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
91 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
92 rs485_deat_dedt_max : rs485_deat_dedt;
93 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
94 USART_CR1_DEDT_MASK;
95 *cr1 |= rs485_deat_dedt;
96}
97
66{
67 u32 rs485_deat_dedt;
68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
69 bool over8;
70
71 *cr3 |= USART_CR3_DEM;
72 over8 = *cr1 & USART_CR1_OVER8;
73

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91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
93 rs485_deat_dedt_max : rs485_deat_dedt;
94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
95 USART_CR1_DEDT_MASK;
96 *cr1 |= rs485_deat_dedt;
97}
98
98static int stm32_config_rs485(struct uart_port *port,
99 struct serial_rs485 *rs485conf)
99static int stm32_usart_config_rs485(struct uart_port *port,
100 struct serial_rs485 *rs485conf)
100{
101 struct stm32_port *stm32_port = to_stm32_port(port);
101{
102 struct stm32_port *stm32_port = to_stm32_port(port);
102 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
103 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
103 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
104 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
104 u32 usartdiv, baud, cr1, cr3;
105 bool over8;
106
105 u32 usartdiv, baud, cr1, cr3;
106 bool over8;
107
107 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
108
109 port->rs485 = *rs485conf;
110
111 rs485conf->flags |= SER_RS485_RX_DURING_TX;
112
113 if (rs485conf->flags & SER_RS485_ENABLED) {
114 cr1 = readl_relaxed(port->membase + ofs->cr1);
115 cr3 = readl_relaxed(port->membase + ofs->cr3);
116 usartdiv = readl_relaxed(port->membase + ofs->brr);
117 usartdiv = usartdiv & GENMASK(15, 0);
118 over8 = cr1 & USART_CR1_OVER8;
119
120 if (over8)
121 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
122 << USART_BRR_04_R_SHIFT;
123
124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
109
110 port->rs485 = *rs485conf;
111
112 rs485conf->flags |= SER_RS485_RX_DURING_TX;
113
114 if (rs485conf->flags & SER_RS485_ENABLED) {
115 cr1 = readl_relaxed(port->membase + ofs->cr1);
116 cr3 = readl_relaxed(port->membase + ofs->cr3);
117 usartdiv = readl_relaxed(port->membase + ofs->brr);
118 usartdiv = usartdiv & GENMASK(15, 0);
119 over8 = cr1 & USART_CR1_OVER8;
120
121 if (over8)
122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
123 << USART_BRR_04_R_SHIFT;
124
125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
125 stm32_config_reg_rs485(&cr1, &cr3,
126 rs485conf->delay_rts_before_send,
127 rs485conf->delay_rts_after_send, baud);
126 stm32_usart_config_reg_rs485(&cr1, &cr3,
127 rs485conf->delay_rts_before_send,
128 rs485conf->delay_rts_after_send,
129 baud);
128
129 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
130 cr3 &= ~USART_CR3_DEP;
131 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
132 } else {
133 cr3 |= USART_CR3_DEP;
134 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
135 }
136
137 writel_relaxed(cr3, port->membase + ofs->cr3);
138 writel_relaxed(cr1, port->membase + ofs->cr1);
139 } else {
130
131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
132 cr3 &= ~USART_CR3_DEP;
133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
134 } else {
135 cr3 |= USART_CR3_DEP;
136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
137 }
138
139 writel_relaxed(cr3, port->membase + ofs->cr3);
140 writel_relaxed(cr1, port->membase + ofs->cr1);
141 } else {
140 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
141 stm32_clr_bits(port, ofs->cr1,
142 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
142 stm32_usart_clr_bits(port, ofs->cr3,
143 USART_CR3_DEM | USART_CR3_DEP);
144 stm32_usart_clr_bits(port, ofs->cr1,
145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
143 }
144
146 }
147
145 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
146
147 return 0;
148}
149
149
150 return 0;
151}
152
150static int stm32_init_rs485(struct uart_port *port,
151 struct platform_device *pdev)
153static int stm32_usart_init_rs485(struct uart_port *port,
154 struct platform_device *pdev)
152{
153 struct serial_rs485 *rs485conf = &port->rs485;
154
155 rs485conf->flags = 0;
156 rs485conf->delay_rts_before_send = 0;
157 rs485conf->delay_rts_after_send = 0;
158
159 if (!pdev->dev.of_node)
160 return -ENODEV;
161
162 return uart_get_rs485_mode(port);
163}
164
155{
156 struct serial_rs485 *rs485conf = &port->rs485;
157
158 rs485conf->flags = 0;
159 rs485conf->delay_rts_before_send = 0;
160 rs485conf->delay_rts_after_send = 0;
161
162 if (!pdev->dev.of_node)
163 return -ENODEV;
164
165 return uart_get_rs485_mode(port);
166}
167
165static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
166 bool threaded)
168static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr,
169 int *last_res, bool threaded)
167{
168 struct stm32_port *stm32_port = to_stm32_port(port);
170{
171 struct stm32_port *stm32_port = to_stm32_port(port);
169 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
172 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
170 enum dma_status status;
171 struct dma_tx_state state;
172
173 *sr = readl_relaxed(port->membase + ofs->isr);
174
175 if (threaded && stm32_port->rx_ch) {
176 status = dmaengine_tx_status(stm32_port->rx_ch,
177 stm32_port->rx_ch->cookie,
178 &state);
173 enum dma_status status;
174 struct dma_tx_state state;
175
176 *sr = readl_relaxed(port->membase + ofs->isr);
177
178 if (threaded && stm32_port->rx_ch) {
179 status = dmaengine_tx_status(stm32_port->rx_ch,
180 stm32_port->rx_ch->cookie,
181 &state);
179 if ((status == DMA_IN_PROGRESS) &&
180 (*last_res != state.residue))
182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue))
181 return 1;
182 else
183 return 0;
184 } else if (*sr & USART_SR_RXNE) {
185 return 1;
186 }
187 return 0;
188}
189
183 return 1;
184 else
185 return 0;
186 } else if (*sr & USART_SR_RXNE) {
187 return 1;
188 }
189 return 0;
190}
191
190static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
191 int *last_res)
192static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr,
193 int *last_res)
192{
193 struct stm32_port *stm32_port = to_stm32_port(port);
194{
195 struct stm32_port *stm32_port = to_stm32_port(port);
194 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
196 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
195 unsigned long c;
196
197 if (stm32_port->rx_ch) {
198 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
199 if ((*last_res) == 0)
200 *last_res = RX_BUF_L;
201 } else {
202 c = readl_relaxed(port->membase + ofs->rdr);
203 /* apply RDR data mask */
204 c &= stm32_port->rdr_mask;
205 }
206
207 return c;
208}
209
197 unsigned long c;
198
199 if (stm32_port->rx_ch) {
200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
201 if ((*last_res) == 0)
202 *last_res = RX_BUF_L;
203 } else {
204 c = readl_relaxed(port->membase + ofs->rdr);
205 /* apply RDR data mask */
206 c &= stm32_port->rdr_mask;
207 }
208
209 return c;
210}
211
210static void stm32_receive_chars(struct uart_port *port, bool threaded)
212static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
211{
212 struct tty_port *tport = &port->state->port;
213 struct stm32_port *stm32_port = to_stm32_port(port);
213{
214 struct tty_port *tport = &port->state->port;
215 struct stm32_port *stm32_port = to_stm32_port(port);
214 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
216 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
215 unsigned long c;
216 u32 sr;
217 char flag;
218
219 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
220 pm_wakeup_event(tport->tty->dev, 0);
221
217 unsigned long c;
218 u32 sr;
219 char flag;
220
221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
222 pm_wakeup_event(tport->tty->dev, 0);
223
222 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
225 threaded)) {
223 sr |= USART_SR_DUMMY_RX;
224 flag = TTY_NORMAL;
225
226 /*
227 * Status bits has to be cleared before reading the RDR:
228 * In FIFO mode, reading the RDR will pop the next data
229 * (if any) along with its status bits into the SR.
230 * Not doing so leads to misalignement between RDR and SR,
231 * and clear status bits of the next rx data.
232 *
233 * Clear errors flags for stm32f7 and stm32h7 compatible
234 * devices. On stm32f4 compatible devices, the error bit is
235 * cleared by the sequence [read SR - read DR].
236 */
237 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
238 writel_relaxed(sr & USART_SR_ERR_MASK,
239 port->membase + ofs->icr);
240
226 sr |= USART_SR_DUMMY_RX;
227 flag = TTY_NORMAL;
228
229 /*
230 * Status bits has to be cleared before reading the RDR:
231 * In FIFO mode, reading the RDR will pop the next data
232 * (if any) along with its status bits into the SR.
233 * Not doing so leads to misalignement between RDR and SR,
234 * and clear status bits of the next rx data.
235 *
236 * Clear errors flags for stm32f7 and stm32h7 compatible
237 * devices. On stm32f4 compatible devices, the error bit is
238 * cleared by the sequence [read SR - read DR].
239 */
240 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
241 writel_relaxed(sr & USART_SR_ERR_MASK,
242 port->membase + ofs->icr);
243
241 c = stm32_get_char(port, &sr, &stm32_port->last_res);
244 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res);
242 port->icount.rx++;
243 if (sr & USART_SR_ERR_MASK) {
244 if (sr & USART_SR_ORE) {
245 port->icount.overrun++;
246 } else if (sr & USART_SR_PE) {
247 port->icount.parity++;
248 } else if (sr & USART_SR_FE) {
249 /* Break detection if character is null */

--- 23 unchanged lines hidden (view full) ---

273 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
274 }
275
276 spin_unlock(&port->lock);
277 tty_flip_buffer_push(tport);
278 spin_lock(&port->lock);
279}
280
245 port->icount.rx++;
246 if (sr & USART_SR_ERR_MASK) {
247 if (sr & USART_SR_ORE) {
248 port->icount.overrun++;
249 } else if (sr & USART_SR_PE) {
250 port->icount.parity++;
251 } else if (sr & USART_SR_FE) {
252 /* Break detection if character is null */

--- 23 unchanged lines hidden (view full) ---

276 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
277 }
278
279 spin_unlock(&port->lock);
280 tty_flip_buffer_push(tport);
281 spin_lock(&port->lock);
282}
283
281static void stm32_tx_dma_complete(void *arg)
284static void stm32_usart_tx_dma_complete(void *arg)
282{
283 struct uart_port *port = arg;
284 struct stm32_port *stm32port = to_stm32_port(port);
285{
286 struct uart_port *port = arg;
287 struct stm32_port *stm32port = to_stm32_port(port);
285 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
288 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
286
289
287 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
290 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
288 stm32port->tx_dma_busy = false;
289
290 /* Let's see if we have pending data to send */
291 stm32port->tx_dma_busy = false;
292
293 /* Let's see if we have pending data to send */
291 stm32_transmit_chars(port);
294 stm32_usart_transmit_chars(port);
292}
293
295}
296
294static void stm32_tx_interrupt_enable(struct uart_port *port)
297static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
295{
296 struct stm32_port *stm32_port = to_stm32_port(port);
298{
299 struct stm32_port *stm32_port = to_stm32_port(port);
297 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
300 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
298
299 /*
300 * Enables TX FIFO threashold irq when FIFO is enabled,
301 * or TX empty irq when FIFO is disabled
302 */
303 if (stm32_port->fifoen)
301
302 /*
303 * Enables TX FIFO threashold irq when FIFO is enabled,
304 * or TX empty irq when FIFO is disabled
305 */
306 if (stm32_port->fifoen)
304 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
307 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
305 else
308 else
306 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
309 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
307}
308
310}
311
309static void stm32_tx_interrupt_disable(struct uart_port *port)
312static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
310{
311 struct stm32_port *stm32_port = to_stm32_port(port);
313{
314 struct stm32_port *stm32_port = to_stm32_port(port);
312 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
315 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
313
314 if (stm32_port->fifoen)
316
317 if (stm32_port->fifoen)
315 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
318 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
316 else
319 else
317 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
320 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
318}
319
321}
322
320static void stm32_transmit_chars_pio(struct uart_port *port)
323static void stm32_usart_transmit_chars_pio(struct uart_port *port)
321{
322 struct stm32_port *stm32_port = to_stm32_port(port);
324{
325 struct stm32_port *stm32_port = to_stm32_port(port);
323 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
326 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
324 struct circ_buf *xmit = &port->state->xmit;
325
326 if (stm32_port->tx_dma_busy) {
327 struct circ_buf *xmit = &port->state->xmit;
328
329 if (stm32_port->tx_dma_busy) {
327 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
330 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
328 stm32_port->tx_dma_busy = false;
329 }
330
331 while (!uart_circ_empty(xmit)) {
332 /* Check that TDR is empty before filling FIFO */
333 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
334 break;
335 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
336 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
337 port->icount.tx++;
338 }
339
340 /* rely on TXE irq (mask or unmask) for sending remaining data */
341 if (uart_circ_empty(xmit))
331 stm32_port->tx_dma_busy = false;
332 }
333
334 while (!uart_circ_empty(xmit)) {
335 /* Check that TDR is empty before filling FIFO */
336 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
337 break;
338 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
339 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
340 port->icount.tx++;
341 }
342
343 /* rely on TXE irq (mask or unmask) for sending remaining data */
344 if (uart_circ_empty(xmit))
342 stm32_tx_interrupt_disable(port);
345 stm32_usart_tx_interrupt_disable(port);
343 else
346 else
344 stm32_tx_interrupt_enable(port);
347 stm32_usart_tx_interrupt_enable(port);
345}
346
348}
349
347static void stm32_transmit_chars_dma(struct uart_port *port)
350static void stm32_usart_transmit_chars_dma(struct uart_port *port)
348{
349 struct stm32_port *stm32port = to_stm32_port(port);
351{
352 struct stm32_port *stm32port = to_stm32_port(port);
350 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
353 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
351 struct circ_buf *xmit = &port->state->xmit;
352 struct dma_async_tx_descriptor *desc = NULL;
353 unsigned int count, i;
354
355 if (stm32port->tx_dma_busy)
356 return;
357
358 stm32port->tx_dma_busy = true;

--- 19 unchanged lines hidden (view full) ---

378 }
379
380 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
381 stm32port->tx_dma_buf,
382 count,
383 DMA_MEM_TO_DEV,
384 DMA_PREP_INTERRUPT);
385
354 struct circ_buf *xmit = &port->state->xmit;
355 struct dma_async_tx_descriptor *desc = NULL;
356 unsigned int count, i;
357
358 if (stm32port->tx_dma_busy)
359 return;
360
361 stm32port->tx_dma_busy = true;

--- 19 unchanged lines hidden (view full) ---

381 }
382
383 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
384 stm32port->tx_dma_buf,
385 count,
386 DMA_MEM_TO_DEV,
387 DMA_PREP_INTERRUPT);
388
386 if (!desc) {
387 for (i = count; i > 0; i--)
388 stm32_transmit_chars_pio(port);
389 return;
390 }
389 if (!desc)
390 goto fallback_err;
391
391
392 desc->callback = stm32_tx_dma_complete;
392 desc->callback = stm32_usart_tx_dma_complete;
393 desc->callback_param = port;
394
395 /* Push current DMA TX transaction in the pending queue */
393 desc->callback_param = port;
394
395 /* Push current DMA TX transaction in the pending queue */
396 dmaengine_submit(desc);
396 if (dma_submit_error(dmaengine_submit(desc))) {
397 /* dma no yet started, safe to free resources */
398 dmaengine_terminate_async(stm32port->tx_ch);
399 goto fallback_err;
400 }
397
398 /* Issue pending DMA TX requests */
399 dma_async_issue_pending(stm32port->tx_ch);
400
401
402 /* Issue pending DMA TX requests */
403 dma_async_issue_pending(stm32port->tx_ch);
404
401 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
405 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
402
403 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
404 port->icount.tx += count;
406
407 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
408 port->icount.tx += count;
409 return;
410
411fallback_err:
412 for (i = count; i > 0; i--)
413 stm32_usart_transmit_chars_pio(port);
405}
406
414}
415
407static void stm32_transmit_chars(struct uart_port *port)
416static void stm32_usart_transmit_chars(struct uart_port *port)
408{
409 struct stm32_port *stm32_port = to_stm32_port(port);
417{
418 struct stm32_port *stm32_port = to_stm32_port(port);
410 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
419 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
411 struct circ_buf *xmit = &port->state->xmit;
412
413 if (port->x_char) {
414 if (stm32_port->tx_dma_busy)
420 struct circ_buf *xmit = &port->state->xmit;
421
422 if (port->x_char) {
423 if (stm32_port->tx_dma_busy)
415 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
424 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
416 writel_relaxed(port->x_char, port->membase + ofs->tdr);
417 port->x_char = 0;
418 port->icount.tx++;
419 if (stm32_port->tx_dma_busy)
425 writel_relaxed(port->x_char, port->membase + ofs->tdr);
426 port->x_char = 0;
427 port->icount.tx++;
428 if (stm32_port->tx_dma_busy)
420 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
429 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
421 return;
422 }
423
424 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
430 return;
431 }
432
433 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
425 stm32_tx_interrupt_disable(port);
434 stm32_usart_tx_interrupt_disable(port);
426 return;
427 }
428
429 if (ofs->icr == UNDEF_REG)
435 return;
436 }
437
438 if (ofs->icr == UNDEF_REG)
430 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
439 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
431 else
432 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
433
434 if (stm32_port->tx_ch)
440 else
441 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
442
443 if (stm32_port->tx_ch)
435 stm32_transmit_chars_dma(port);
444 stm32_usart_transmit_chars_dma(port);
436 else
445 else
437 stm32_transmit_chars_pio(port);
446 stm32_usart_transmit_chars_pio(port);
438
439 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
440 uart_write_wakeup(port);
441
442 if (uart_circ_empty(xmit))
447
448 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
449 uart_write_wakeup(port);
450
451 if (uart_circ_empty(xmit))
443 stm32_tx_interrupt_disable(port);
452 stm32_usart_tx_interrupt_disable(port);
444}
445
453}
454
446static irqreturn_t stm32_interrupt(int irq, void *ptr)
455static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
447{
448 struct uart_port *port = ptr;
449 struct stm32_port *stm32_port = to_stm32_port(port);
456{
457 struct uart_port *port = ptr;
458 struct stm32_port *stm32_port = to_stm32_port(port);
450 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
459 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
451 u32 sr;
452
453 spin_lock(&port->lock);
454
455 sr = readl_relaxed(port->membase + ofs->isr);
456
457 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
458 writel_relaxed(USART_ICR_RTOCF,
459 port->membase + ofs->icr);
460
460 u32 sr;
461
462 spin_lock(&port->lock);
463
464 sr = readl_relaxed(port->membase + ofs->isr);
465
466 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
467 writel_relaxed(USART_ICR_RTOCF,
468 port->membase + ofs->icr);
469
461 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
470 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG)
462 writel_relaxed(USART_ICR_WUCF,
463 port->membase + ofs->icr);
464
465 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
471 writel_relaxed(USART_ICR_WUCF,
472 port->membase + ofs->icr);
473
474 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
466 stm32_receive_chars(port, false);
475 stm32_usart_receive_chars(port, false);
467
468 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
476
477 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
469 stm32_transmit_chars(port);
478 stm32_usart_transmit_chars(port);
470
471 spin_unlock(&port->lock);
472
473 if (stm32_port->rx_ch)
474 return IRQ_WAKE_THREAD;
475 else
476 return IRQ_HANDLED;
477}
478
479
480 spin_unlock(&port->lock);
481
482 if (stm32_port->rx_ch)
483 return IRQ_WAKE_THREAD;
484 else
485 return IRQ_HANDLED;
486}
487
479static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
488static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
480{
481 struct uart_port *port = ptr;
482 struct stm32_port *stm32_port = to_stm32_port(port);
483
484 spin_lock(&port->lock);
485
486 if (stm32_port->rx_ch)
489{
490 struct uart_port *port = ptr;
491 struct stm32_port *stm32_port = to_stm32_port(port);
492
493 spin_lock(&port->lock);
494
495 if (stm32_port->rx_ch)
487 stm32_receive_chars(port, true);
496 stm32_usart_receive_chars(port, true);
488
489 spin_unlock(&port->lock);
490
491 return IRQ_HANDLED;
492}
493
497
498 spin_unlock(&port->lock);
499
500 return IRQ_HANDLED;
501}
502
494static unsigned int stm32_tx_empty(struct uart_port *port)
503static unsigned int stm32_usart_tx_empty(struct uart_port *port)
495{
496 struct stm32_port *stm32_port = to_stm32_port(port);
504{
505 struct stm32_port *stm32_port = to_stm32_port(port);
497 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
506 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
498
499 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
500}
501
507
508 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
509}
510
502static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
511static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
503{
504 struct stm32_port *stm32_port = to_stm32_port(port);
512{
513 struct stm32_port *stm32_port = to_stm32_port(port);
505 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
514 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
506
507 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
515
516 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
508 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
517 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
509 else
518 else
510 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
519 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
511
512 mctrl_gpio_set(stm32_port->gpios, mctrl);
513}
514
520
521 mctrl_gpio_set(stm32_port->gpios, mctrl);
522}
523
515static unsigned int stm32_get_mctrl(struct uart_port *port)
524static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
516{
517 struct stm32_port *stm32_port = to_stm32_port(port);
518 unsigned int ret;
519
520 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
521 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
522
523 return mctrl_gpio_get(stm32_port->gpios, &ret);
524}
525
525{
526 struct stm32_port *stm32_port = to_stm32_port(port);
527 unsigned int ret;
528
529 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
530 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
531
532 return mctrl_gpio_get(stm32_port->gpios, &ret);
533}
534
526static void stm32_enable_ms(struct uart_port *port)
535static void stm32_usart_enable_ms(struct uart_port *port)
527{
528 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
529}
530
536{
537 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
538}
539
531static void stm32_disable_ms(struct uart_port *port)
540static void stm32_usart_disable_ms(struct uart_port *port)
532{
533 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
534}
535
536/* Transmit stop */
541{
542 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
543}
544
545/* Transmit stop */
537static void stm32_stop_tx(struct uart_port *port)
546static void stm32_usart_stop_tx(struct uart_port *port)
538{
539 struct stm32_port *stm32_port = to_stm32_port(port);
540 struct serial_rs485 *rs485conf = &port->rs485;
541
547{
548 struct stm32_port *stm32_port = to_stm32_port(port);
549 struct serial_rs485 *rs485conf = &port->rs485;
550
542 stm32_tx_interrupt_disable(port);
551 stm32_usart_tx_interrupt_disable(port);
543
544 if (rs485conf->flags & SER_RS485_ENABLED) {
545 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
546 mctrl_gpio_set(stm32_port->gpios,
547 stm32_port->port.mctrl & ~TIOCM_RTS);
548 } else {
549 mctrl_gpio_set(stm32_port->gpios,
550 stm32_port->port.mctrl | TIOCM_RTS);
551 }
552 }
553}
554
555/* There are probably characters waiting to be transmitted. */
552
553 if (rs485conf->flags & SER_RS485_ENABLED) {
554 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
555 mctrl_gpio_set(stm32_port->gpios,
556 stm32_port->port.mctrl & ~TIOCM_RTS);
557 } else {
558 mctrl_gpio_set(stm32_port->gpios,
559 stm32_port->port.mctrl | TIOCM_RTS);
560 }
561 }
562}
563
564/* There are probably characters waiting to be transmitted. */
556static void stm32_start_tx(struct uart_port *port)
565static void stm32_usart_start_tx(struct uart_port *port)
557{
558 struct stm32_port *stm32_port = to_stm32_port(port);
559 struct serial_rs485 *rs485conf = &port->rs485;
560 struct circ_buf *xmit = &port->state->xmit;
561
562 if (uart_circ_empty(xmit))
563 return;
564
565 if (rs485conf->flags & SER_RS485_ENABLED) {
566 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
567 mctrl_gpio_set(stm32_port->gpios,
568 stm32_port->port.mctrl | TIOCM_RTS);
569 } else {
570 mctrl_gpio_set(stm32_port->gpios,
571 stm32_port->port.mctrl & ~TIOCM_RTS);
572 }
573 }
574
566{
567 struct stm32_port *stm32_port = to_stm32_port(port);
568 struct serial_rs485 *rs485conf = &port->rs485;
569 struct circ_buf *xmit = &port->state->xmit;
570
571 if (uart_circ_empty(xmit))
572 return;
573
574 if (rs485conf->flags & SER_RS485_ENABLED) {
575 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
576 mctrl_gpio_set(stm32_port->gpios,
577 stm32_port->port.mctrl | TIOCM_RTS);
578 } else {
579 mctrl_gpio_set(stm32_port->gpios,
580 stm32_port->port.mctrl & ~TIOCM_RTS);
581 }
582 }
583
575 stm32_transmit_chars(port);
584 stm32_usart_transmit_chars(port);
576}
577
578/* Throttle the remote when input buffer is about to overflow. */
585}
586
587/* Throttle the remote when input buffer is about to overflow. */
579static void stm32_throttle(struct uart_port *port)
588static void stm32_usart_throttle(struct uart_port *port)
580{
581 struct stm32_port *stm32_port = to_stm32_port(port);
589{
590 struct stm32_port *stm32_port = to_stm32_port(port);
582 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
591 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
583 unsigned long flags;
584
585 spin_lock_irqsave(&port->lock, flags);
592 unsigned long flags;
593
594 spin_lock_irqsave(&port->lock, flags);
586 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
595 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
587 if (stm32_port->cr3_irq)
596 if (stm32_port->cr3_irq)
588 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
597 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
589
590 spin_unlock_irqrestore(&port->lock, flags);
591}
592
593/* Unthrottle the remote, the input buffer can now accept data. */
598
599 spin_unlock_irqrestore(&port->lock, flags);
600}
601
602/* Unthrottle the remote, the input buffer can now accept data. */
594static void stm32_unthrottle(struct uart_port *port)
603static void stm32_usart_unthrottle(struct uart_port *port)
595{
596 struct stm32_port *stm32_port = to_stm32_port(port);
604{
605 struct stm32_port *stm32_port = to_stm32_port(port);
597 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
606 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
598 unsigned long flags;
599
600 spin_lock_irqsave(&port->lock, flags);
607 unsigned long flags;
608
609 spin_lock_irqsave(&port->lock, flags);
601 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
610 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
602 if (stm32_port->cr3_irq)
611 if (stm32_port->cr3_irq)
603 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
612 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
604
605 spin_unlock_irqrestore(&port->lock, flags);
606}
607
608/* Receive stop */
613
614 spin_unlock_irqrestore(&port->lock, flags);
615}
616
617/* Receive stop */
609static void stm32_stop_rx(struct uart_port *port)
618static void stm32_usart_stop_rx(struct uart_port *port)
610{
611 struct stm32_port *stm32_port = to_stm32_port(port);
619{
620 struct stm32_port *stm32_port = to_stm32_port(port);
612 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
621 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
613
622
614 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
623 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
615 if (stm32_port->cr3_irq)
624 if (stm32_port->cr3_irq)
616 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
617
625 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
618}
619
620/* Handle breaks - ignored by us */
626}
627
628/* Handle breaks - ignored by us */
621static void stm32_break_ctl(struct uart_port *port, int break_state)
629static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
622{
623}
624
630{
631}
632
625static int stm32_startup(struct uart_port *port)
633static int stm32_usart_startup(struct uart_port *port)
626{
627 struct stm32_port *stm32_port = to_stm32_port(port);
634{
635 struct stm32_port *stm32_port = to_stm32_port(port);
628 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
636 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
629 const char *name = to_platform_device(port->dev)->name;
630 u32 val;
631 int ret;
632
637 const char *name = to_platform_device(port->dev)->name;
638 u32 val;
639 int ret;
640
633 ret = request_threaded_irq(port->irq, stm32_interrupt,
634 stm32_threaded_interrupt,
641 ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
642 stm32_usart_threaded_interrupt,
635 IRQF_NO_SUSPEND, name, port);
636 if (ret)
637 return ret;
638
639 /* RX FIFO Flush */
640 if (ofs->rqr != UNDEF_REG)
643 IRQF_NO_SUSPEND, name, port);
644 if (ret)
645 return ret;
646
647 /* RX FIFO Flush */
648 if (ofs->rqr != UNDEF_REG)
641 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
649 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
642
643 /* Tx and RX FIFO configuration */
644 if (stm32_port->fifoen) {
645 val = readl_relaxed(port->membase + ofs->cr3);
646 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
647 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
648 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
649 writel_relaxed(val, port->membase + ofs->cr3);
650 }
651
652 /* RX FIFO enabling */
653 val = stm32_port->cr1_irq | USART_CR1_RE;
654 if (stm32_port->fifoen)
655 val |= USART_CR1_FIFOEN;
650
651 /* Tx and RX FIFO configuration */
652 if (stm32_port->fifoen) {
653 val = readl_relaxed(port->membase + ofs->cr3);
654 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
655 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
656 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
657 writel_relaxed(val, port->membase + ofs->cr3);
658 }
659
660 /* RX FIFO enabling */
661 val = stm32_port->cr1_irq | USART_CR1_RE;
662 if (stm32_port->fifoen)
663 val |= USART_CR1_FIFOEN;
656 stm32_set_bits(port, ofs->cr1, val);
664 stm32_usart_set_bits(port, ofs->cr1, val);
657
658 return 0;
659}
660
665
666 return 0;
667}
668
661static void stm32_shutdown(struct uart_port *port)
669static void stm32_usart_shutdown(struct uart_port *port)
662{
663 struct stm32_port *stm32_port = to_stm32_port(port);
670{
671 struct stm32_port *stm32_port = to_stm32_port(port);
664 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
665 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
672 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
673 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
666 u32 val, isr;
667 int ret;
668
669 /* Disable modem control interrupts */
674 u32 val, isr;
675 int ret;
676
677 /* Disable modem control interrupts */
670 stm32_disable_ms(port);
678 stm32_usart_disable_ms(port);
671
672 val = USART_CR1_TXEIE | USART_CR1_TE;
673 val |= stm32_port->cr1_irq | USART_CR1_RE;
674 val |= BIT(cfg->uart_enable_bit);
675 if (stm32_port->fifoen)
676 val |= USART_CR1_FIFOEN;
677
678 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
679 isr, (isr & USART_SR_TC),
680 10, 100000);
681
679
680 val = USART_CR1_TXEIE | USART_CR1_TE;
681 val |= stm32_port->cr1_irq | USART_CR1_RE;
682 val |= BIT(cfg->uart_enable_bit);
683 if (stm32_port->fifoen)
684 val |= USART_CR1_FIFOEN;
685
686 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
687 isr, (isr & USART_SR_TC),
688 10, 100000);
689
690 /* Send the TC error message only when ISR_TC is not set */
682 if (ret)
691 if (ret)
683 dev_err(port->dev, "transmission complete not set\n");
692 dev_err(port->dev, "Transmission is not complete\n");
684
693
685 stm32_clr_bits(port, ofs->cr1, val);
694 stm32_usart_clr_bits(port, ofs->cr1, val);
686
687 free_irq(port->irq, port);
688}
689
695
696 free_irq(port->irq, port);
697}
698
690static unsigned int stm32_get_databits(struct ktermios *termios)
699static unsigned int stm32_usart_get_databits(struct ktermios *termios)
691{
692 unsigned int bits;
693
694 tcflag_t cflag = termios->c_cflag;
695
696 switch (cflag & CSIZE) {
697 /*
698 * CSIZE settings are not necessarily supported in hardware.

--- 13 unchanged lines hidden (view full) ---

712 default:
713 bits = 8;
714 break;
715 }
716
717 return bits;
718}
719
700{
701 unsigned int bits;
702
703 tcflag_t cflag = termios->c_cflag;
704
705 switch (cflag & CSIZE) {
706 /*
707 * CSIZE settings are not necessarily supported in hardware.

--- 13 unchanged lines hidden (view full) ---

721 default:
722 bits = 8;
723 break;
724 }
725
726 return bits;
727}
728
720static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
721 struct ktermios *old)
729static void stm32_usart_set_termios(struct uart_port *port,
730 struct ktermios *termios,
731 struct ktermios *old)
722{
723 struct stm32_port *stm32_port = to_stm32_port(port);
732{
733 struct stm32_port *stm32_port = to_stm32_port(port);
724 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
725 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
734 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
735 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
726 struct serial_rs485 *rs485conf = &port->rs485;
727 unsigned int baud, bits;
728 u32 usartdiv, mantissa, fraction, oversampling;
729 tcflag_t cflag = termios->c_cflag;
730 u32 cr1, cr2, cr3;
731 unsigned long flags;
732
733 if (!stm32_port->hw_flow_control)
734 cflag &= ~CRTSCTS;
735
736 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
737
738 spin_lock_irqsave(&port->lock, flags);
739
740 /* Stop serial port and reset value */
741 writel_relaxed(0, port->membase + ofs->cr1);
742
743 /* flush RX & TX FIFO */
744 if (ofs->rqr != UNDEF_REG)
736 struct serial_rs485 *rs485conf = &port->rs485;
737 unsigned int baud, bits;
738 u32 usartdiv, mantissa, fraction, oversampling;
739 tcflag_t cflag = termios->c_cflag;
740 u32 cr1, cr2, cr3;
741 unsigned long flags;
742
743 if (!stm32_port->hw_flow_control)
744 cflag &= ~CRTSCTS;
745
746 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
747
748 spin_lock_irqsave(&port->lock, flags);
749
750 /* Stop serial port and reset value */
751 writel_relaxed(0, port->membase + ofs->cr1);
752
753 /* flush RX & TX FIFO */
754 if (ofs->rqr != UNDEF_REG)
745 stm32_set_bits(port, ofs->rqr,
746 USART_RQR_TXFRQ | USART_RQR_RXFRQ);
755 stm32_usart_set_bits(port, ofs->rqr,
756 USART_RQR_TXFRQ | USART_RQR_RXFRQ);
747
748 cr1 = USART_CR1_TE | USART_CR1_RE;
749 if (stm32_port->fifoen)
750 cr1 |= USART_CR1_FIFOEN;
751 cr2 = 0;
752 cr3 = readl_relaxed(port->membase + ofs->cr3);
753 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
754 | USART_CR3_TXFTCFG_MASK;
755
756 if (cflag & CSTOPB)
757 cr2 |= USART_CR2_STOP_2B;
758
757
758 cr1 = USART_CR1_TE | USART_CR1_RE;
759 if (stm32_port->fifoen)
760 cr1 |= USART_CR1_FIFOEN;
761 cr2 = 0;
762 cr3 = readl_relaxed(port->membase + ofs->cr3);
763 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
764 | USART_CR3_TXFTCFG_MASK;
765
766 if (cflag & CSTOPB)
767 cr2 |= USART_CR2_STOP_2B;
768
759 bits = stm32_get_databits(termios);
769 bits = stm32_usart_get_databits(termios);
760 stm32_port->rdr_mask = (BIT(bits) - 1);
761
762 if (cflag & PARENB) {
763 bits++;
764 cr1 |= USART_CR1_PCE;
765 }
766
767 /*

--- 36 unchanged lines hidden (view full) ---

804 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
805 if (cflag & CRTSCTS) {
806 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
807 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
808 }
809
810 /* Handle modem control interrupts */
811 if (UART_ENABLE_MS(port, termios->c_cflag))
770 stm32_port->rdr_mask = (BIT(bits) - 1);
771
772 if (cflag & PARENB) {
773 bits++;
774 cr1 |= USART_CR1_PCE;
775 }
776
777 /*

--- 36 unchanged lines hidden (view full) ---

814 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
815 if (cflag & CRTSCTS) {
816 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
817 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
818 }
819
820 /* Handle modem control interrupts */
821 if (UART_ENABLE_MS(port, termios->c_cflag))
812 stm32_enable_ms(port);
822 stm32_usart_enable_ms(port);
813 else
823 else
814 stm32_disable_ms(port);
824 stm32_usart_disable_ms(port);
815
816 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
817
818 /*
819 * The USART supports 16 or 8 times oversampling.
820 * By default we prefer 16 times oversampling, so that the receiver
821 * has a better tolerance to clock deviations.
822 * 8 times oversampling is only used to achieve higher speeds.
823 */
824 if (usartdiv < 16) {
825 oversampling = 8;
826 cr1 |= USART_CR1_OVER8;
825
826 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
827
828 /*
829 * The USART supports 16 or 8 times oversampling.
830 * By default we prefer 16 times oversampling, so that the receiver
831 * has a better tolerance to clock deviations.
832 * 8 times oversampling is only used to achieve higher speeds.
833 */
834 if (usartdiv < 16) {
835 oversampling = 8;
836 cr1 |= USART_CR1_OVER8;
827 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
837 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
828 } else {
829 oversampling = 16;
830 cr1 &= ~USART_CR1_OVER8;
838 } else {
839 oversampling = 16;
840 cr1 &= ~USART_CR1_OVER8;
831 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
841 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
832 }
833
834 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
835 fraction = usartdiv % oversampling;
836 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
837
838 uart_update_timeout(port, cflag, baud);
839

--- 20 unchanged lines hidden (view full) ---

860 /* Ignore all characters if CREAD is not set */
861 if ((termios->c_cflag & CREAD) == 0)
862 port->ignore_status_mask |= USART_SR_DUMMY_RX;
863
864 if (stm32_port->rx_ch)
865 cr3 |= USART_CR3_DMAR;
866
867 if (rs485conf->flags & SER_RS485_ENABLED) {
842 }
843
844 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
845 fraction = usartdiv % oversampling;
846 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
847
848 uart_update_timeout(port, cflag, baud);
849

--- 20 unchanged lines hidden (view full) ---

870 /* Ignore all characters if CREAD is not set */
871 if ((termios->c_cflag & CREAD) == 0)
872 port->ignore_status_mask |= USART_SR_DUMMY_RX;
873
874 if (stm32_port->rx_ch)
875 cr3 |= USART_CR3_DMAR;
876
877 if (rs485conf->flags & SER_RS485_ENABLED) {
868 stm32_config_reg_rs485(&cr1, &cr3,
869 rs485conf->delay_rts_before_send,
870 rs485conf->delay_rts_after_send, baud);
878 stm32_usart_config_reg_rs485(&cr1, &cr3,
879 rs485conf->delay_rts_before_send,
880 rs485conf->delay_rts_after_send,
881 baud);
871 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
872 cr3 &= ~USART_CR3_DEP;
873 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
874 } else {
875 cr3 |= USART_CR3_DEP;
876 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
877 }
878
879 } else {
880 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
881 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
882 }
883
884 writel_relaxed(cr3, port->membase + ofs->cr3);
885 writel_relaxed(cr2, port->membase + ofs->cr2);
886 writel_relaxed(cr1, port->membase + ofs->cr1);
887
882 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
883 cr3 &= ~USART_CR3_DEP;
884 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
885 } else {
886 cr3 |= USART_CR3_DEP;
887 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
888 }
889
890 } else {
891 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
892 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
893 }
894
895 writel_relaxed(cr3, port->membase + ofs->cr3);
896 writel_relaxed(cr2, port->membase + ofs->cr2);
897 writel_relaxed(cr1, port->membase + ofs->cr1);
898
888 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
899 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
889 spin_unlock_irqrestore(&port->lock, flags);
890}
891
900 spin_unlock_irqrestore(&port->lock, flags);
901}
902
892static const char *stm32_type(struct uart_port *port)
903static const char *stm32_usart_type(struct uart_port *port)
893{
894 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
895}
896
904{
905 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
906}
907
897static void stm32_release_port(struct uart_port *port)
908static void stm32_usart_release_port(struct uart_port *port)
898{
899}
900
909{
910}
911
901static int stm32_request_port(struct uart_port *port)
912static int stm32_usart_request_port(struct uart_port *port)
902{
903 return 0;
904}
905
913{
914 return 0;
915}
916
906static void stm32_config_port(struct uart_port *port, int flags)
917static void stm32_usart_config_port(struct uart_port *port, int flags)
907{
908 if (flags & UART_CONFIG_TYPE)
909 port->type = PORT_STM32;
910}
911
912static int
918{
919 if (flags & UART_CONFIG_TYPE)
920 port->type = PORT_STM32;
921}
922
923static int
913stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
924stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
914{
915 /* No user changeable parameters */
916 return -EINVAL;
917}
918
925{
926 /* No user changeable parameters */
927 return -EINVAL;
928}
929
919static void stm32_pm(struct uart_port *port, unsigned int state,
920 unsigned int oldstate)
930static void stm32_usart_pm(struct uart_port *port, unsigned int state,
931 unsigned int oldstate)
921{
922 struct stm32_port *stm32port = container_of(port,
923 struct stm32_port, port);
932{
933 struct stm32_port *stm32port = container_of(port,
934 struct stm32_port, port);
924 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
925 const struct stm32_usart_config *cfg = &stm32port->info->cfg;
935 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
936 struct stm32_usart_config *cfg = &stm32port->info->cfg;
926 unsigned long flags = 0;
927
928 switch (state) {
929 case UART_PM_STATE_ON:
930 pm_runtime_get_sync(port->dev);
931 break;
932 case UART_PM_STATE_OFF:
933 spin_lock_irqsave(&port->lock, flags);
937 unsigned long flags = 0;
938
939 switch (state) {
940 case UART_PM_STATE_ON:
941 pm_runtime_get_sync(port->dev);
942 break;
943 case UART_PM_STATE_OFF:
944 spin_lock_irqsave(&port->lock, flags);
934 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
945 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
935 spin_unlock_irqrestore(&port->lock, flags);
936 pm_runtime_put_sync(port->dev);
937 break;
938 }
939}
940
941static const struct uart_ops stm32_uart_ops = {
946 spin_unlock_irqrestore(&port->lock, flags);
947 pm_runtime_put_sync(port->dev);
948 break;
949 }
950}
951
952static const struct uart_ops stm32_uart_ops = {
942 .tx_empty = stm32_tx_empty,
943 .set_mctrl = stm32_set_mctrl,
944 .get_mctrl = stm32_get_mctrl,
945 .stop_tx = stm32_stop_tx,
946 .start_tx = stm32_start_tx,
947 .throttle = stm32_throttle,
948 .unthrottle = stm32_unthrottle,
949 .stop_rx = stm32_stop_rx,
950 .enable_ms = stm32_enable_ms,
951 .break_ctl = stm32_break_ctl,
952 .startup = stm32_startup,
953 .shutdown = stm32_shutdown,
954 .set_termios = stm32_set_termios,
955 .pm = stm32_pm,
956 .type = stm32_type,
957 .release_port = stm32_release_port,
958 .request_port = stm32_request_port,
959 .config_port = stm32_config_port,
960 .verify_port = stm32_verify_port,
953 .tx_empty = stm32_usart_tx_empty,
954 .set_mctrl = stm32_usart_set_mctrl,
955 .get_mctrl = stm32_usart_get_mctrl,
956 .stop_tx = stm32_usart_stop_tx,
957 .start_tx = stm32_usart_start_tx,
958 .throttle = stm32_usart_throttle,
959 .unthrottle = stm32_usart_unthrottle,
960 .stop_rx = stm32_usart_stop_rx,
961 .enable_ms = stm32_usart_enable_ms,
962 .break_ctl = stm32_usart_break_ctl,
963 .startup = stm32_usart_startup,
964 .shutdown = stm32_usart_shutdown,
965 .set_termios = stm32_usart_set_termios,
966 .pm = stm32_usart_pm,
967 .type = stm32_usart_type,
968 .release_port = stm32_usart_release_port,
969 .request_port = stm32_usart_request_port,
970 .config_port = stm32_usart_config_port,
971 .verify_port = stm32_usart_verify_port,
961};
962
972};
973
963static int stm32_init_port(struct stm32_port *stm32port,
964 struct platform_device *pdev)
974static void stm32_usart_deinit_port(struct stm32_port *stm32port)
965{
975{
976 clk_disable_unprepare(stm32port->clk);
977}
978
979static int stm32_usart_init_port(struct stm32_port *stm32port,
980 struct platform_device *pdev)
981{
966 struct uart_port *port = &stm32port->port;
967 struct resource *res;
982 struct uart_port *port = &stm32port->port;
983 struct resource *res;
968 int ret;
984 int ret, irq;
969
985
986 irq = platform_get_irq(pdev, 0);
987 if (irq <= 0)
988 return irq ? : -ENODEV;
989
970 port->iotype = UPIO_MEM;
971 port->flags = UPF_BOOT_AUTOCONF;
972 port->ops = &stm32_uart_ops;
973 port->dev = &pdev->dev;
974 port->fifosize = stm32port->info->cfg.fifosize;
975 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
990 port->iotype = UPIO_MEM;
991 port->flags = UPF_BOOT_AUTOCONF;
992 port->ops = &stm32_uart_ops;
993 port->dev = &pdev->dev;
994 port->fifosize = stm32port->info->cfg.fifosize;
995 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
996 port->irq = irq;
997 port->rs485_config = stm32_usart_config_rs485;
976
998
977 ret = platform_get_irq(pdev, 0);
978 if (ret <= 0)
979 return ret ? : -ENODEV;
980 port->irq = ret;
981
982 port->rs485_config = stm32_config_rs485;
983
984 ret = stm32_init_rs485(port, pdev);
999 ret = stm32_usart_init_rs485(port, pdev);
985 if (ret)
986 return ret;
987
988 if (stm32port->info->cfg.has_wakeup) {
989 stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
990 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
991 return stm32port->wakeirq ? : -ENODEV;
992 }

--- 24 unchanged lines hidden (view full) ---

1017 }
1018
1019 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1020 if (IS_ERR(stm32port->gpios)) {
1021 ret = PTR_ERR(stm32port->gpios);
1022 goto err_clk;
1023 }
1024
1000 if (ret)
1001 return ret;
1002
1003 if (stm32port->info->cfg.has_wakeup) {
1004 stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
1005 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
1006 return stm32port->wakeirq ? : -ENODEV;
1007 }

--- 24 unchanged lines hidden (view full) ---

1032 }
1033
1034 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1035 if (IS_ERR(stm32port->gpios)) {
1036 ret = PTR_ERR(stm32port->gpios);
1037 goto err_clk;
1038 }
1039
1025 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */
1040 /*
1041 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts"
1042 * properties should not be specified.
1043 */
1026 if (stm32port->hw_flow_control) {
1027 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1028 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1029 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1030 ret = -EINVAL;
1031 goto err_clk;
1032 }
1033 }
1034
1035 return ret;
1036
1037err_clk:
1038 clk_disable_unprepare(stm32port->clk);
1039
1040 return ret;
1041}
1042
1044 if (stm32port->hw_flow_control) {
1045 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1046 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1047 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1048 ret = -EINVAL;
1049 goto err_clk;
1050 }
1051 }
1052
1053 return ret;
1054
1055err_clk:
1056 clk_disable_unprepare(stm32port->clk);
1057
1058 return ret;
1059}
1060
1043static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
1061static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1044{
1045 struct device_node *np = pdev->dev.of_node;
1046 int id;
1047
1048 if (!np)
1049 return NULL;
1050
1051 id = of_alias_get_id(np, "serial");

--- 21 unchanged lines hidden (view full) ---

1073 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1074 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1075 {},
1076};
1077
1078MODULE_DEVICE_TABLE(of, stm32_match);
1079#endif
1080
1062{
1063 struct device_node *np = pdev->dev.of_node;
1064 int id;
1065
1066 if (!np)
1067 return NULL;
1068
1069 id = of_alias_get_id(np, "serial");

--- 21 unchanged lines hidden (view full) ---

1091 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1092 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1093 {},
1094};
1095
1096MODULE_DEVICE_TABLE(of, stm32_match);
1097#endif
1098
1081static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
1082 struct platform_device *pdev)
1099static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1100 struct platform_device *pdev)
1083{
1101{
1084 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1102 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1085 struct uart_port *port = &stm32port->port;
1086 struct device *dev = &pdev->dev;
1087 struct dma_slave_config config;
1088 struct dma_async_tx_descriptor *desc = NULL;
1089 int ret;
1090
1091 /* Request DMA RX channel */
1092 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1093 if (!stm32port->rx_ch) {
1094 dev_info(dev, "rx dma alloc failed\n");
1095 return -ENODEV;
1096 }
1097 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1103 struct uart_port *port = &stm32port->port;
1104 struct device *dev = &pdev->dev;
1105 struct dma_slave_config config;
1106 struct dma_async_tx_descriptor *desc = NULL;
1107 int ret;
1108
1109 /* Request DMA RX channel */
1110 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1111 if (!stm32port->rx_ch) {
1112 dev_info(dev, "rx dma alloc failed\n");
1113 return -ENODEV;
1114 }
1115 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1098 &stm32port->rx_dma_buf,
1099 GFP_KERNEL);
1116 &stm32port->rx_dma_buf,
1117 GFP_KERNEL);
1100 if (!stm32port->rx_buf) {
1101 ret = -ENOMEM;
1102 goto alloc_err;
1103 }
1104
1105 /* Configure DMA channel */
1106 memset(&config, 0, sizeof(config));
1107 config.src_addr = port->mapbase + ofs->rdr;

--- 17 unchanged lines hidden (view full) ---

1125 goto config_err;
1126 }
1127
1128 /* No callback as dma buffer is drained on usart interrupt */
1129 desc->callback = NULL;
1130 desc->callback_param = NULL;
1131
1132 /* Push current DMA transaction in the pending queue */
1118 if (!stm32port->rx_buf) {
1119 ret = -ENOMEM;
1120 goto alloc_err;
1121 }
1122
1123 /* Configure DMA channel */
1124 memset(&config, 0, sizeof(config));
1125 config.src_addr = port->mapbase + ofs->rdr;

--- 17 unchanged lines hidden (view full) ---

1143 goto config_err;
1144 }
1145
1146 /* No callback as dma buffer is drained on usart interrupt */
1147 desc->callback = NULL;
1148 desc->callback_param = NULL;
1149
1150 /* Push current DMA transaction in the pending queue */
1133 dmaengine_submit(desc);
1151 ret = dma_submit_error(dmaengine_submit(desc));
1152 if (ret) {
1153 dmaengine_terminate_sync(stm32port->rx_ch);
1154 goto config_err;
1155 }
1134
1135 /* Issue pending DMA requests */
1136 dma_async_issue_pending(stm32port->rx_ch);
1137
1138 return 0;
1139
1140config_err:
1141 dma_free_coherent(&pdev->dev,
1142 RX_BUF_L, stm32port->rx_buf,
1143 stm32port->rx_dma_buf);
1144
1145alloc_err:
1146 dma_release_channel(stm32port->rx_ch);
1147 stm32port->rx_ch = NULL;
1148
1149 return ret;
1150}
1151
1156
1157 /* Issue pending DMA requests */
1158 dma_async_issue_pending(stm32port->rx_ch);
1159
1160 return 0;
1161
1162config_err:
1163 dma_free_coherent(&pdev->dev,
1164 RX_BUF_L, stm32port->rx_buf,
1165 stm32port->rx_dma_buf);
1166
1167alloc_err:
1168 dma_release_channel(stm32port->rx_ch);
1169 stm32port->rx_ch = NULL;
1170
1171 return ret;
1172}
1173
1152static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1153 struct platform_device *pdev)
1174static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1175 struct platform_device *pdev)
1154{
1176{
1155 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1177 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1156 struct uart_port *port = &stm32port->port;
1157 struct device *dev = &pdev->dev;
1158 struct dma_slave_config config;
1159 int ret;
1160
1161 stm32port->tx_dma_busy = false;
1162
1163 /* Request DMA TX channel */
1164 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1165 if (!stm32port->tx_ch) {
1166 dev_info(dev, "tx dma alloc failed\n");
1167 return -ENODEV;
1168 }
1169 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1178 struct uart_port *port = &stm32port->port;
1179 struct device *dev = &pdev->dev;
1180 struct dma_slave_config config;
1181 int ret;
1182
1183 stm32port->tx_dma_busy = false;
1184
1185 /* Request DMA TX channel */
1186 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1187 if (!stm32port->tx_ch) {
1188 dev_info(dev, "tx dma alloc failed\n");
1189 return -ENODEV;
1190 }
1191 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1170 &stm32port->tx_dma_buf,
1171 GFP_KERNEL);
1192 &stm32port->tx_dma_buf,
1193 GFP_KERNEL);
1172 if (!stm32port->tx_buf) {
1173 ret = -ENOMEM;
1174 goto alloc_err;
1175 }
1176
1177 /* Configure DMA channel */
1178 memset(&config, 0, sizeof(config));
1179 config.dst_addr = port->mapbase + ofs->tdr;

--- 15 unchanged lines hidden (view full) ---

1195
1196alloc_err:
1197 dma_release_channel(stm32port->tx_ch);
1198 stm32port->tx_ch = NULL;
1199
1200 return ret;
1201}
1202
1194 if (!stm32port->tx_buf) {
1195 ret = -ENOMEM;
1196 goto alloc_err;
1197 }
1198
1199 /* Configure DMA channel */
1200 memset(&config, 0, sizeof(config));
1201 config.dst_addr = port->mapbase + ofs->tdr;

--- 15 unchanged lines hidden (view full) ---

1217
1218alloc_err:
1219 dma_release_channel(stm32port->tx_ch);
1220 stm32port->tx_ch = NULL;
1221
1222 return ret;
1223}
1224
1203static int stm32_serial_probe(struct platform_device *pdev)
1225static int stm32_usart_serial_probe(struct platform_device *pdev)
1204{
1226{
1227 const struct of_device_id *match;
1205 struct stm32_port *stm32port;
1206 int ret;
1207
1228 struct stm32_port *stm32port;
1229 int ret;
1230
1208 stm32port = stm32_of_get_stm32_port(pdev);
1231 stm32port = stm32_usart_of_get_port(pdev);
1209 if (!stm32port)
1210 return -ENODEV;
1211
1232 if (!stm32port)
1233 return -ENODEV;
1234
1212 stm32port->info = of_device_get_match_data(&pdev->dev);
1213 if (!stm32port->info)
1235 match = of_match_device(stm32_match, &pdev->dev);
1236 if (match && match->data)
1237 stm32port->info = (struct stm32_usart_info *)match->data;
1238 else
1214 return -EINVAL;
1215
1239 return -EINVAL;
1240
1216 ret = stm32_init_port(stm32port, pdev);
1241 ret = stm32_usart_init_port(stm32port, pdev);
1217 if (ret)
1218 return ret;
1219
1220 if (stm32port->wakeirq > 0) {
1221 ret = device_init_wakeup(&pdev->dev, true);
1222 if (ret)
1223 goto err_uninit;
1224

--- 4 unchanged lines hidden (view full) ---

1229
1230 device_set_wakeup_enable(&pdev->dev, false);
1231 }
1232
1233 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1234 if (ret)
1235 goto err_wirq;
1236
1242 if (ret)
1243 return ret;
1244
1245 if (stm32port->wakeirq > 0) {
1246 ret = device_init_wakeup(&pdev->dev, true);
1247 if (ret)
1248 goto err_uninit;
1249

--- 4 unchanged lines hidden (view full) ---

1254
1255 device_set_wakeup_enable(&pdev->dev, false);
1256 }
1257
1258 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1259 if (ret)
1260 goto err_wirq;
1261
1237 ret = stm32_of_dma_rx_probe(stm32port, pdev);
1262 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
1238 if (ret)
1239 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1240
1263 if (ret)
1264 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1265
1241 ret = stm32_of_dma_tx_probe(stm32port, pdev);
1266 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
1242 if (ret)
1243 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1244
1245 platform_set_drvdata(pdev, &stm32port->port);
1246
1247 pm_runtime_get_noresume(&pdev->dev);
1248 pm_runtime_set_active(&pdev->dev);
1249 pm_runtime_enable(&pdev->dev);

--- 5 unchanged lines hidden (view full) ---

1255 if (stm32port->wakeirq > 0)
1256 dev_pm_clear_wake_irq(&pdev->dev);
1257
1258err_nowup:
1259 if (stm32port->wakeirq > 0)
1260 device_init_wakeup(&pdev->dev, false);
1261
1262err_uninit:
1267 if (ret)
1268 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1269
1270 platform_set_drvdata(pdev, &stm32port->port);
1271
1272 pm_runtime_get_noresume(&pdev->dev);
1273 pm_runtime_set_active(&pdev->dev);
1274 pm_runtime_enable(&pdev->dev);

--- 5 unchanged lines hidden (view full) ---

1280 if (stm32port->wakeirq > 0)
1281 dev_pm_clear_wake_irq(&pdev->dev);
1282
1283err_nowup:
1284 if (stm32port->wakeirq > 0)
1285 device_init_wakeup(&pdev->dev, false);
1286
1287err_uninit:
1263 clk_disable_unprepare(stm32port->clk);
1288 stm32_usart_deinit_port(stm32port);
1264
1265 return ret;
1266}
1267
1289
1290 return ret;
1291}
1292
1268static int stm32_serial_remove(struct platform_device *pdev)
1293static int stm32_usart_serial_remove(struct platform_device *pdev)
1269{
1270 struct uart_port *port = platform_get_drvdata(pdev);
1271 struct stm32_port *stm32_port = to_stm32_port(port);
1294{
1295 struct uart_port *port = platform_get_drvdata(pdev);
1296 struct stm32_port *stm32_port = to_stm32_port(port);
1272 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1297 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1273 int err;
1274
1275 pm_runtime_get_sync(&pdev->dev);
1276
1298 int err;
1299
1300 pm_runtime_get_sync(&pdev->dev);
1301
1277 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1302 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1278
1279 if (stm32_port->rx_ch)
1280 dma_release_channel(stm32_port->rx_ch);
1281
1282 if (stm32_port->rx_dma_buf)
1283 dma_free_coherent(&pdev->dev,
1284 RX_BUF_L, stm32_port->rx_buf,
1285 stm32_port->rx_dma_buf);
1286
1303
1304 if (stm32_port->rx_ch)
1305 dma_release_channel(stm32_port->rx_ch);
1306
1307 if (stm32_port->rx_dma_buf)
1308 dma_free_coherent(&pdev->dev,
1309 RX_BUF_L, stm32_port->rx_buf,
1310 stm32_port->rx_dma_buf);
1311
1287 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1312 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1288
1289 if (stm32_port->tx_ch)
1290 dma_release_channel(stm32_port->tx_ch);
1291
1292 if (stm32_port->tx_dma_buf)
1293 dma_free_coherent(&pdev->dev,
1294 TX_BUF_L, stm32_port->tx_buf,
1295 stm32_port->tx_dma_buf);
1296
1297 if (stm32_port->wakeirq > 0) {
1298 dev_pm_clear_wake_irq(&pdev->dev);
1299 device_init_wakeup(&pdev->dev, false);
1300 }
1301
1313
1314 if (stm32_port->tx_ch)
1315 dma_release_channel(stm32_port->tx_ch);
1316
1317 if (stm32_port->tx_dma_buf)
1318 dma_free_coherent(&pdev->dev,
1319 TX_BUF_L, stm32_port->tx_buf,
1320 stm32_port->tx_dma_buf);
1321
1322 if (stm32_port->wakeirq > 0) {
1323 dev_pm_clear_wake_irq(&pdev->dev);
1324 device_init_wakeup(&pdev->dev, false);
1325 }
1326
1302 clk_disable_unprepare(stm32_port->clk);
1327 stm32_usart_deinit_port(stm32_port);
1303
1304 err = uart_remove_one_port(&stm32_usart_driver, port);
1305
1306 pm_runtime_disable(&pdev->dev);
1307 pm_runtime_put_noidle(&pdev->dev);
1308
1309 return err;
1310}
1311
1328
1329 err = uart_remove_one_port(&stm32_usart_driver, port);
1330
1331 pm_runtime_disable(&pdev->dev);
1332 pm_runtime_put_noidle(&pdev->dev);
1333
1334 return err;
1335}
1336
1312
1313#ifdef CONFIG_SERIAL_STM32_CONSOLE
1337#ifdef CONFIG_SERIAL_STM32_CONSOLE
1314static void stm32_console_putchar(struct uart_port *port, int ch)
1338static void stm32_usart_console_putchar(struct uart_port *port, int ch)
1315{
1316 struct stm32_port *stm32_port = to_stm32_port(port);
1339{
1340 struct stm32_port *stm32_port = to_stm32_port(port);
1317 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1341 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1318
1319 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1320 cpu_relax();
1321
1322 writel_relaxed(ch, port->membase + ofs->tdr);
1323}
1324
1342
1343 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1344 cpu_relax();
1345
1346 writel_relaxed(ch, port->membase + ofs->tdr);
1347}
1348
1325static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1349static void stm32_usart_console_write(struct console *co, const char *s,
1350 unsigned int cnt)
1326{
1327 struct uart_port *port = &stm32_ports[co->index].port;
1328 struct stm32_port *stm32_port = to_stm32_port(port);
1351{
1352 struct uart_port *port = &stm32_ports[co->index].port;
1353 struct stm32_port *stm32_port = to_stm32_port(port);
1329 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1330 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1354 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1355 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1331 unsigned long flags;
1332 u32 old_cr1, new_cr1;
1333 int locked = 1;
1334
1335 local_irq_save(flags);
1336 if (port->sysrq)
1337 locked = 0;
1338 else if (oops_in_progress)
1339 locked = spin_trylock(&port->lock);
1340 else
1341 spin_lock(&port->lock);
1342
1343 /* Save and disable interrupts, enable the transmitter */
1344 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1345 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1346 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1347 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1348
1356 unsigned long flags;
1357 u32 old_cr1, new_cr1;
1358 int locked = 1;
1359
1360 local_irq_save(flags);
1361 if (port->sysrq)
1362 locked = 0;
1363 else if (oops_in_progress)
1364 locked = spin_trylock(&port->lock);
1365 else
1366 spin_lock(&port->lock);
1367
1368 /* Save and disable interrupts, enable the transmitter */
1369 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1370 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1371 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1372 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1373
1349 uart_console_write(port, s, cnt, stm32_console_putchar);
1374 uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1350
1351 /* Restore interrupt state */
1352 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1353
1354 if (locked)
1355 spin_unlock(&port->lock);
1356 local_irq_restore(flags);
1357}
1358
1375
1376 /* Restore interrupt state */
1377 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1378
1379 if (locked)
1380 spin_unlock(&port->lock);
1381 local_irq_restore(flags);
1382}
1383
1359static int stm32_console_setup(struct console *co, char *options)
1384static int stm32_usart_console_setup(struct console *co, char *options)
1360{
1361 struct stm32_port *stm32port;
1362 int baud = 9600;
1363 int bits = 8;
1364 int parity = 'n';
1365 int flow = 'n';
1366
1367 if (co->index >= STM32_MAX_PORTS)
1368 return -ENODEV;
1369
1370 stm32port = &stm32_ports[co->index];
1371
1372 /*
1373 * This driver does not support early console initialization
1374 * (use ARM early printk support instead), so we only expect
1375 * this to be called during the uart port registration when the
1376 * driver gets probed and the port should be mapped at that point.
1377 */
1385{
1386 struct stm32_port *stm32port;
1387 int baud = 9600;
1388 int bits = 8;
1389 int parity = 'n';
1390 int flow = 'n';
1391
1392 if (co->index >= STM32_MAX_PORTS)
1393 return -ENODEV;
1394
1395 stm32port = &stm32_ports[co->index];
1396
1397 /*
1398 * This driver does not support early console initialization
1399 * (use ARM early printk support instead), so we only expect
1400 * this to be called during the uart port registration when the
1401 * driver gets probed and the port should be mapped at that point.
1402 */
1378 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1403 if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1379 return -ENXIO;
1380
1381 if (options)
1382 uart_parse_options(options, &baud, &parity, &bits, &flow);
1383
1384 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1385}
1386
1387static struct console stm32_console = {
1388 .name = STM32_SERIAL_NAME,
1389 .device = uart_console_device,
1404 return -ENXIO;
1405
1406 if (options)
1407 uart_parse_options(options, &baud, &parity, &bits, &flow);
1408
1409 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1410}
1411
1412static struct console stm32_console = {
1413 .name = STM32_SERIAL_NAME,
1414 .device = uart_console_device,
1390 .write = stm32_console_write,
1391 .setup = stm32_console_setup,
1415 .write = stm32_usart_console_write,
1416 .setup = stm32_usart_console_setup,
1392 .flags = CON_PRINTBUFFER,
1393 .index = -1,
1394 .data = &stm32_usart_driver,
1395};
1396
1397#define STM32_SERIAL_CONSOLE (&stm32_console)
1398
1399#else

--- 4 unchanged lines hidden (view full) ---

1404 .driver_name = DRIVER_NAME,
1405 .dev_name = STM32_SERIAL_NAME,
1406 .major = 0,
1407 .minor = 0,
1408 .nr = STM32_MAX_PORTS,
1409 .cons = STM32_SERIAL_CONSOLE,
1410};
1411
1417 .flags = CON_PRINTBUFFER,
1418 .index = -1,
1419 .data = &stm32_usart_driver,
1420};
1421
1422#define STM32_SERIAL_CONSOLE (&stm32_console)
1423
1424#else

--- 4 unchanged lines hidden (view full) ---

1429 .driver_name = DRIVER_NAME,
1430 .dev_name = STM32_SERIAL_NAME,
1431 .major = 0,
1432 .minor = 0,
1433 .nr = STM32_MAX_PORTS,
1434 .cons = STM32_SERIAL_CONSOLE,
1435};
1436
1412static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port,
1413 bool enable)
1437static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1438 bool enable)
1414{
1415 struct stm32_port *stm32_port = to_stm32_port(port);
1439{
1440 struct stm32_port *stm32_port = to_stm32_port(port);
1416 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1417 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1441 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1442 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1418 u32 val;
1419
1420 if (stm32_port->wakeirq <= 0)
1421 return;
1422
1423 if (enable) {
1443 u32 val;
1444
1445 if (stm32_port->wakeirq <= 0)
1446 return;
1447
1448 if (enable) {
1424 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1425 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1449 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1450 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1426 val = readl_relaxed(port->membase + ofs->cr3);
1427 val &= ~USART_CR3_WUS_MASK;
1428 /* Enable Wake up interrupt from low power on start bit */
1429 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1430 writel_relaxed(val, port->membase + ofs->cr3);
1451 val = readl_relaxed(port->membase + ofs->cr3);
1452 val &= ~USART_CR3_WUS_MASK;
1453 /* Enable Wake up interrupt from low power on start bit */
1454 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1455 writel_relaxed(val, port->membase + ofs->cr3);
1431 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1456 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1432 } else {
1457 } else {
1433 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1458 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1434 }
1435}
1436
1459 }
1460}
1461
1437static int __maybe_unused stm32_serial_suspend(struct device *dev)
1462static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
1438{
1439 struct uart_port *port = dev_get_drvdata(dev);
1440
1441 uart_suspend_port(&stm32_usart_driver, port);
1442
1443 if (device_may_wakeup(dev))
1463{
1464 struct uart_port *port = dev_get_drvdata(dev);
1465
1466 uart_suspend_port(&stm32_usart_driver, port);
1467
1468 if (device_may_wakeup(dev))
1444 stm32_serial_enable_wakeup(port, true);
1469 stm32_usart_serial_en_wakeup(port, true);
1445 else
1470 else
1446 stm32_serial_enable_wakeup(port, false);
1471 stm32_usart_serial_en_wakeup(port, false);
1447
1448 /*
1449 * When "no_console_suspend" is enabled, keep the pinctrl default state
1450 * and rely on bootloader stage to restore this state upon resume.
1451 * Otherwise, apply the idle or sleep states depending on wakeup
1452 * capabilities.
1453 */
1454 if (console_suspend_enabled || !uart_console(port)) {
1455 if (device_may_wakeup(dev))
1456 pinctrl_pm_select_idle_state(dev);
1457 else
1458 pinctrl_pm_select_sleep_state(dev);
1459 }
1460
1461 return 0;
1462}
1463
1472
1473 /*
1474 * When "no_console_suspend" is enabled, keep the pinctrl default state
1475 * and rely on bootloader stage to restore this state upon resume.
1476 * Otherwise, apply the idle or sleep states depending on wakeup
1477 * capabilities.
1478 */
1479 if (console_suspend_enabled || !uart_console(port)) {
1480 if (device_may_wakeup(dev))
1481 pinctrl_pm_select_idle_state(dev);
1482 else
1483 pinctrl_pm_select_sleep_state(dev);
1484 }
1485
1486 return 0;
1487}
1488
1464static int __maybe_unused stm32_serial_resume(struct device *dev)
1489static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
1465{
1466 struct uart_port *port = dev_get_drvdata(dev);
1467
1468 pinctrl_pm_select_default_state(dev);
1469
1470 if (device_may_wakeup(dev))
1490{
1491 struct uart_port *port = dev_get_drvdata(dev);
1492
1493 pinctrl_pm_select_default_state(dev);
1494
1495 if (device_may_wakeup(dev))
1471 stm32_serial_enable_wakeup(port, false);
1496 stm32_usart_serial_en_wakeup(port, false);
1472
1473 return uart_resume_port(&stm32_usart_driver, port);
1474}
1475
1497
1498 return uart_resume_port(&stm32_usart_driver, port);
1499}
1500
1476static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev)
1501static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1477{
1478 struct uart_port *port = dev_get_drvdata(dev);
1479 struct stm32_port *stm32port = container_of(port,
1480 struct stm32_port, port);
1481
1482 clk_disable_unprepare(stm32port->clk);
1483
1484 return 0;
1485}
1486
1502{
1503 struct uart_port *port = dev_get_drvdata(dev);
1504 struct stm32_port *stm32port = container_of(port,
1505 struct stm32_port, port);
1506
1507 clk_disable_unprepare(stm32port->clk);
1508
1509 return 0;
1510}
1511
1487static int __maybe_unused stm32_serial_runtime_resume(struct device *dev)
1512static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
1488{
1489 struct uart_port *port = dev_get_drvdata(dev);
1490 struct stm32_port *stm32port = container_of(port,
1491 struct stm32_port, port);
1492
1493 return clk_prepare_enable(stm32port->clk);
1494}
1495
1496static const struct dev_pm_ops stm32_serial_pm_ops = {
1513{
1514 struct uart_port *port = dev_get_drvdata(dev);
1515 struct stm32_port *stm32port = container_of(port,
1516 struct stm32_port, port);
1517
1518 return clk_prepare_enable(stm32port->clk);
1519}
1520
1521static const struct dev_pm_ops stm32_serial_pm_ops = {
1497 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend,
1498 stm32_serial_runtime_resume, NULL)
1499 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1522 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
1523 stm32_usart_runtime_resume, NULL)
1524 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
1525 stm32_usart_serial_resume)
1500};
1501
1502static struct platform_driver stm32_serial_driver = {
1526};
1527
1528static struct platform_driver stm32_serial_driver = {
1503 .probe = stm32_serial_probe,
1504 .remove = stm32_serial_remove,
1529 .probe = stm32_usart_serial_probe,
1530 .remove = stm32_usart_serial_remove,
1505 .driver = {
1506 .name = DRIVER_NAME,
1507 .pm = &stm32_serial_pm_ops,
1508 .of_match_table = of_match_ptr(stm32_match),
1509 },
1510};
1511
1531 .driver = {
1532 .name = DRIVER_NAME,
1533 .pm = &stm32_serial_pm_ops,
1534 .of_match_table = of_match_ptr(stm32_match),
1535 },
1536};
1537
1512static int __init usart_init(void)
1538static int __init stm32_usart_init(void)
1513{
1514 static char banner[] __initdata = "STM32 USART driver initialized";
1515 int ret;
1516
1517 pr_info("%s\n", banner);
1518
1519 ret = uart_register_driver(&stm32_usart_driver);
1520 if (ret)
1521 return ret;
1522
1523 ret = platform_driver_register(&stm32_serial_driver);
1524 if (ret)
1525 uart_unregister_driver(&stm32_usart_driver);
1526
1527 return ret;
1528}
1529
1539{
1540 static char banner[] __initdata = "STM32 USART driver initialized";
1541 int ret;
1542
1543 pr_info("%s\n", banner);
1544
1545 ret = uart_register_driver(&stm32_usart_driver);
1546 if (ret)
1547 return ret;
1548
1549 ret = platform_driver_register(&stm32_serial_driver);
1550 if (ret)
1551 uart_unregister_driver(&stm32_usart_driver);
1552
1553 return ret;
1554}
1555
1530static void __exit usart_exit(void)
1556static void __exit stm32_usart_exit(void)
1531{
1532 platform_driver_unregister(&stm32_serial_driver);
1533 uart_unregister_driver(&stm32_usart_driver);
1534}
1535
1557{
1558 platform_driver_unregister(&stm32_serial_driver);
1559 uart_unregister_driver(&stm32_usart_driver);
1560}
1561
1536module_init(usart_init);
1537module_exit(usart_exit);
1562module_init(stm32_usart_init);
1563module_exit(stm32_usart_exit);
1538
1539MODULE_ALIAS("platform:" DRIVER_NAME);
1540MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1541MODULE_LICENSE("GPL v2");
1564
1565MODULE_ALIAS("platform:" DRIVER_NAME);
1566MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1567MODULE_LICENSE("GPL v2");