stm32-usart.c (96d3c5a7d20ec546e44695983fe0508c6f904248) stm32-usart.c (9f9be0ec3130066c5c0bd85da260fa96ea46fd6a)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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852static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
853{
854 struct uart_port *port = ptr;
855 struct tty_port *tport = &port->state->port;
856 struct stm32_port *stm32_port = to_stm32_port(port);
857 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
858 u32 sr;
859 unsigned int size;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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852static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
853{
854 struct uart_port *port = ptr;
855 struct tty_port *tport = &port->state->port;
856 struct stm32_port *stm32_port = to_stm32_port(port);
857 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
858 u32 sr;
859 unsigned int size;
860 irqreturn_t ret = IRQ_NONE;
860
861 sr = readl_relaxed(port->membase + ofs->isr);
862
863 if (!stm32_port->hw_flow_control &&
864 port->rs485.flags & SER_RS485_ENABLED &&
865 (sr & USART_SR_TC)) {
866 stm32_usart_tc_interrupt_disable(port);
867 stm32_usart_rs485_rts_disable(port);
861
862 sr = readl_relaxed(port->membase + ofs->isr);
863
864 if (!stm32_port->hw_flow_control &&
865 port->rs485.flags & SER_RS485_ENABLED &&
866 (sr & USART_SR_TC)) {
867 stm32_usart_tc_interrupt_disable(port);
868 stm32_usart_rs485_rts_disable(port);
869 ret = IRQ_HANDLED;
868 }
869
870 }
871
870 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
872 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) {
871 writel_relaxed(USART_ICR_RTOCF,
872 port->membase + ofs->icr);
873 writel_relaxed(USART_ICR_RTOCF,
874 port->membase + ofs->icr);
875 ret = IRQ_HANDLED;
876 }
873
874 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
875 /* Clear wake up flag and disable wake up interrupt */
876 writel_relaxed(USART_ICR_WUCF,
877 port->membase + ofs->icr);
878 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
879 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
880 pm_wakeup_event(tport->tty->dev, 0);
877
878 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
879 /* Clear wake up flag and disable wake up interrupt */
880 writel_relaxed(USART_ICR_WUCF,
881 port->membase + ofs->icr);
882 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
883 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
884 pm_wakeup_event(tport->tty->dev, 0);
885 ret = IRQ_HANDLED;
881 }
882
883 /*
884 * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request
885 * line has been masked by HW and rx data are stacking in FIFO.
886 */
887 if (!stm32_port->throttled) {
888 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) ||
889 ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) {
890 spin_lock(&port->lock);
891 size = stm32_usart_receive_chars(port, false);
892 uart_unlock_and_check_sysrq(port);
893 if (size)
894 tty_flip_buffer_push(tport);
886 }
887
888 /*
889 * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request
890 * line has been masked by HW and rx data are stacking in FIFO.
891 */
892 if (!stm32_port->throttled) {
893 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) ||
894 ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) {
895 spin_lock(&port->lock);
896 size = stm32_usart_receive_chars(port, false);
897 uart_unlock_and_check_sysrq(port);
898 if (size)
899 tty_flip_buffer_push(tport);
900 ret = IRQ_HANDLED;
895 }
896 }
897
898 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
899 spin_lock(&port->lock);
900 stm32_usart_transmit_chars(port);
901 spin_unlock(&port->lock);
901 }
902 }
903
904 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
905 spin_lock(&port->lock);
906 stm32_usart_transmit_chars(port);
907 spin_unlock(&port->lock);
908 ret = IRQ_HANDLED;
902 }
903
904 /* Receiver timeout irq for DMA RX */
905 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) {
906 spin_lock(&port->lock);
907 size = stm32_usart_receive_chars(port, false);
908 uart_unlock_and_check_sysrq(port);
909 if (size)
910 tty_flip_buffer_push(tport);
909 }
910
911 /* Receiver timeout irq for DMA RX */
912 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) {
913 spin_lock(&port->lock);
914 size = stm32_usart_receive_chars(port, false);
915 uart_unlock_and_check_sysrq(port);
916 if (size)
917 tty_flip_buffer_push(tport);
918 ret = IRQ_HANDLED;
911 }
912
919 }
920
913 return IRQ_HANDLED;
921 return ret;
914}
915
916static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
917{
918 struct stm32_port *stm32_port = to_stm32_port(port);
919 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
920
921 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))

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923
924static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
925{
926 struct stm32_port *stm32_port = to_stm32_port(port);
927 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
928
929 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))

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