stm32-usart.c (56a23f9319e86e1d62a109896e2c7e52c414e67d) stm32-usart.c (9a135f16d228857c5c1212a58050196883343d1e)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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360 }
361 } else {
362 size = stm32_usart_receive_chars_pio(port);
363 }
364
365 return size;
366}
367
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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360 }
361 } else {
362 size = stm32_usart_receive_chars_pio(port);
363 }
364
365 return size;
366}
367
368static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
369{
370 dmaengine_terminate_async(stm32_port->tx_ch);
371 stm32_port->tx_dma_busy = false;
372}
373
374static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
375{
376 /*
377 * We cannot use the function "dmaengine_tx_status" to know the
378 * status of DMA. This function does not show if the "dma complete"
379 * callback of the DMA transaction has been called. So we prefer
380 * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
381 * same time.
382 */
383 return stm32_port->tx_dma_busy;
384}
385
386static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port)
387{
388 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
389
390 return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT);
391}
392
368static void stm32_usart_tx_dma_complete(void *arg)
369{
370 struct uart_port *port = arg;
371 struct stm32_port *stm32port = to_stm32_port(port);
372 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
373 unsigned long flags;
374
393static void stm32_usart_tx_dma_complete(void *arg)
394{
395 struct uart_port *port = arg;
396 struct stm32_port *stm32port = to_stm32_port(port);
397 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
398 unsigned long flags;
399
375 dmaengine_terminate_async(stm32port->tx_ch);
376 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
400 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
377 stm32port->tx_dma_busy = false;
401 stm32_usart_tx_dma_terminate(stm32port);
378
379 /* Let's see if we have pending data to send */
380 spin_lock_irqsave(&port->lock, flags);
381 stm32_usart_transmit_chars(port);
382 spin_unlock_irqrestore(&port->lock, flags);
383}
384
385static void stm32_usart_tx_interrupt_enable(struct uart_port *port)

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423}
424
425static void stm32_usart_transmit_chars_pio(struct uart_port *port)
426{
427 struct stm32_port *stm32_port = to_stm32_port(port);
428 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
429 struct circ_buf *xmit = &port->state->xmit;
430
402
403 /* Let's see if we have pending data to send */
404 spin_lock_irqsave(&port->lock, flags);
405 stm32_usart_transmit_chars(port);
406 spin_unlock_irqrestore(&port->lock, flags);
407}
408
409static void stm32_usart_tx_interrupt_enable(struct uart_port *port)

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447}
448
449static void stm32_usart_transmit_chars_pio(struct uart_port *port)
450{
451 struct stm32_port *stm32_port = to_stm32_port(port);
452 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
453 struct circ_buf *xmit = &port->state->xmit;
454
431 if (stm32_port->tx_dma_busy) {
455 if (stm32_usart_tx_dma_enabled(stm32_port))
432 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
456 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
433 stm32_port->tx_dma_busy = false;
434 }
435
436 while (!uart_circ_empty(xmit)) {
437 /* Check that TDR is empty before filling FIFO */
438 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
439 break;
440 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
441 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
442 port->icount.tx++;

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452static void stm32_usart_transmit_chars_dma(struct uart_port *port)
453{
454 struct stm32_port *stm32port = to_stm32_port(port);
455 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
456 struct circ_buf *xmit = &port->state->xmit;
457 struct dma_async_tx_descriptor *desc = NULL;
458 unsigned int count, i;
459
457
458 while (!uart_circ_empty(xmit)) {
459 /* Check that TDR is empty before filling FIFO */
460 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
461 break;
462 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
463 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
464 port->icount.tx++;

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474static void stm32_usart_transmit_chars_dma(struct uart_port *port)
475{
476 struct stm32_port *stm32port = to_stm32_port(port);
477 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
478 struct circ_buf *xmit = &port->state->xmit;
479 struct dma_async_tx_descriptor *desc = NULL;
480 unsigned int count, i;
481
460 if (stm32port->tx_dma_busy)
482 if (stm32_usart_tx_dma_started(stm32port)) {
483 if (!stm32_usart_tx_dma_enabled(stm32port))
484 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
461 return;
485 return;
486 }
462
487
463 stm32port->tx_dma_busy = true;
464
465 count = uart_circ_chars_pending(xmit);
466
467 if (count > TX_BUF_L)
468 count = TX_BUF_L;
469
470 if (xmit->tail < xmit->head) {
471 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
472 } else {

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486 stm32port->tx_dma_buf,
487 count,
488 DMA_MEM_TO_DEV,
489 DMA_PREP_INTERRUPT);
490
491 if (!desc)
492 goto fallback_err;
493
488 count = uart_circ_chars_pending(xmit);
489
490 if (count > TX_BUF_L)
491 count = TX_BUF_L;
492
493 if (xmit->tail < xmit->head) {
494 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
495 } else {

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509 stm32port->tx_dma_buf,
510 count,
511 DMA_MEM_TO_DEV,
512 DMA_PREP_INTERRUPT);
513
514 if (!desc)
515 goto fallback_err;
516
517 /*
518 * Set "tx_dma_busy" flag. This flag will be released when
519 * dmaengine_terminate_async will be called. This flag helps
520 * transmit_chars_dma not to start another DMA transaction
521 * if the callback of the previous is not yet called.
522 */
523 stm32port->tx_dma_busy = true;
524
494 desc->callback = stm32_usart_tx_dma_complete;
495 desc->callback_param = port;
496
497 /* Push current DMA TX transaction in the pending queue */
498 if (dma_submit_error(dmaengine_submit(desc))) {
499 /* dma no yet started, safe to free resources */
525 desc->callback = stm32_usart_tx_dma_complete;
526 desc->callback_param = port;
527
528 /* Push current DMA TX transaction in the pending queue */
529 if (dma_submit_error(dmaengine_submit(desc))) {
530 /* dma no yet started, safe to free resources */
500 dmaengine_terminate_async(stm32port->tx_ch);
531 stm32_usart_tx_dma_terminate(stm32port);
501 goto fallback_err;
502 }
503
504 /* Issue pending DMA TX requests */
505 dma_async_issue_pending(stm32port->tx_ch);
506
507 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
508

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517
518static void stm32_usart_transmit_chars(struct uart_port *port)
519{
520 struct stm32_port *stm32_port = to_stm32_port(port);
521 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
522 struct circ_buf *xmit = &port->state->xmit;
523
524 if (port->x_char) {
532 goto fallback_err;
533 }
534
535 /* Issue pending DMA TX requests */
536 dma_async_issue_pending(stm32port->tx_ch);
537
538 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
539

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548
549static void stm32_usart_transmit_chars(struct uart_port *port)
550{
551 struct stm32_port *stm32_port = to_stm32_port(port);
552 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
553 struct circ_buf *xmit = &port->state->xmit;
554
555 if (port->x_char) {
525 if (stm32_port->tx_dma_busy)
556 if (stm32_usart_tx_dma_started(stm32_port) &&
557 stm32_usart_tx_dma_enabled(stm32_port))
526 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
527 writel_relaxed(port->x_char, port->membase + ofs->tdr);
528 port->x_char = 0;
529 port->icount.tx++;
558 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
559 writel_relaxed(port->x_char, port->membase + ofs->tdr);
560 port->x_char = 0;
561 port->icount.tx++;
530 if (stm32_port->tx_dma_busy)
562 if (stm32_usart_tx_dma_started(stm32_port))
531 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
532 return;
533 }
534
535 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
536 stm32_usart_tx_interrupt_disable(port);
537 return;
538 }

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714
715/* Flush the transmit buffer. */
716static void stm32_usart_flush_buffer(struct uart_port *port)
717{
718 struct stm32_port *stm32_port = to_stm32_port(port);
719 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
720
721 if (stm32_port->tx_ch) {
563 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
564 return;
565 }
566
567 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
568 stm32_usart_tx_interrupt_disable(port);
569 return;
570 }

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746
747/* Flush the transmit buffer. */
748static void stm32_usart_flush_buffer(struct uart_port *port)
749{
750 struct stm32_port *stm32_port = to_stm32_port(port);
751 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
752
753 if (stm32_port->tx_ch) {
722 dmaengine_terminate_async(stm32_port->tx_ch);
754 stm32_usart_tx_dma_terminate(stm32_port);
723 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
755 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
724 stm32_port->tx_dma_busy = false;
725 }
726}
727
728/* Throttle the remote when input buffer is about to overflow. */
729static void stm32_usart_throttle(struct uart_port *port)
730{
731 struct stm32_port *stm32_port = to_stm32_port(port);
732 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;

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878static void stm32_usart_shutdown(struct uart_port *port)
879{
880 struct stm32_port *stm32_port = to_stm32_port(port);
881 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
882 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
883 u32 val, isr;
884 int ret;
885
756 }
757}
758
759/* Throttle the remote when input buffer is about to overflow. */
760static void stm32_usart_throttle(struct uart_port *port)
761{
762 struct stm32_port *stm32_port = to_stm32_port(port);
763 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;

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909static void stm32_usart_shutdown(struct uart_port *port)
910{
911 struct stm32_port *stm32_port = to_stm32_port(port);
912 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
913 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
914 u32 val, isr;
915 int ret;
916
886 if (stm32_port->tx_dma_busy) {
887 dmaengine_terminate_async(stm32_port->tx_ch);
917 if (stm32_usart_tx_dma_enabled(stm32_port))
888 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
918 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
889 }
890
919
920 if (stm32_usart_tx_dma_started(stm32_port))
921 stm32_usart_tx_dma_terminate(stm32_port);
922
891 /* Disable modem control interrupts */
892 stm32_usart_disable_ms(port);
893
894 val = USART_CR1_TXEIE | USART_CR1_TE;
895 val |= stm32_port->cr1_irq | USART_CR1_RE;
896 val |= BIT(cfg->uart_enable_bit);
897 if (stm32_port->fifoen)
898 val |= USART_CR1_FIFOEN;

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1419 struct platform_device *pdev)
1420{
1421 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1422 struct uart_port *port = &stm32port->port;
1423 struct device *dev = &pdev->dev;
1424 struct dma_slave_config config;
1425 int ret;
1426
923 /* Disable modem control interrupts */
924 stm32_usart_disable_ms(port);
925
926 val = USART_CR1_TXEIE | USART_CR1_TE;
927 val |= stm32_port->cr1_irq | USART_CR1_RE;
928 val |= BIT(cfg->uart_enable_bit);
929 if (stm32_port->fifoen)
930 val |= USART_CR1_FIFOEN;

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1451 struct platform_device *pdev)
1452{
1453 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1454 struct uart_port *port = &stm32port->port;
1455 struct device *dev = &pdev->dev;
1456 struct dma_slave_config config;
1457 int ret;
1458
1427 stm32port->tx_dma_busy = false;
1428
1429 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
1430 &stm32port->tx_dma_buf,
1431 GFP_KERNEL);
1432 if (!stm32port->tx_buf)
1433 return -ENOMEM;
1434
1435 /* Configure DMA channel */
1436 memset(&config, 0, sizeof(config));

--- 424 unchanged lines hidden --- 		1459 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
1460 &stm32port->tx_dma_buf,
1461 GFP_KERNEL);
1462 if (!stm32port->tx_buf)
1463 return -ENOMEM;
1464
1465 /* Configure DMA channel */
1466 memset(&config, 0, sizeof(config));

--- 424 unchanged lines hidden ---