stm32-usart.c (2612e3bbc0386368a850140a6c9b990cd496a5ec) stm32-usart.c (db89728abad5ab6b8f30349142897bd55f1f5b00)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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316 /* Handle only RX data errors when using DMA */
317 if (*sr & USART_SR_ERR_MASK)
318 return true;
319 }
320
321 return false;
322}
323
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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316 /* Handle only RX data errors when using DMA */
317 if (*sr & USART_SR_ERR_MASK)
318 return true;
319 }
320
321 return false;
322}
323
324static unsigned long stm32_usart_get_char_pio(struct uart_port *port)
324static u8 stm32_usart_get_char_pio(struct uart_port *port)
325{
326 struct stm32_port *stm32_port = to_stm32_port(port);
327 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
328 unsigned long c;
329
330 c = readl_relaxed(port->membase + ofs->rdr);
331 /* Apply RDR data mask */
332 c &= stm32_port->rdr_mask;
333
334 return c;
335}
336
337static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port)
338{
339 struct stm32_port *stm32_port = to_stm32_port(port);
340 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
325{
326 struct stm32_port *stm32_port = to_stm32_port(port);
327 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
328 unsigned long c;
329
330 c = readl_relaxed(port->membase + ofs->rdr);
331 /* Apply RDR data mask */
332 c &= stm32_port->rdr_mask;
333
334 return c;
335}
336
337static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port)
338{
339 struct stm32_port *stm32_port = to_stm32_port(port);
340 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
341 unsigned long c;
342 unsigned int size = 0;
343 u32 sr;
341 unsigned int size = 0;
342 u32 sr;
344 char flag;
343 u8 c, flag;
345
346 while (stm32_usart_pending_rx_pio(port, &sr)) {
347 sr |= USART_SR_DUMMY_RX;
348 flag = TTY_NORMAL;
349
350 /*
351 * Status bits has to be cleared before reading the RDR:
352 * In FIFO mode, reading the RDR will pop the next data

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502 * status of DMA. This function does not show if the "dma complete"
503 * callback of the DMA transaction has been called. So we prefer
504 * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
505 * same time.
506 */
507 return stm32_port->tx_dma_busy;
508}
509
344
345 while (stm32_usart_pending_rx_pio(port, &sr)) {
346 sr |= USART_SR_DUMMY_RX;
347 flag = TTY_NORMAL;
348
349 /*
350 * Status bits has to be cleared before reading the RDR:
351 * In FIFO mode, reading the RDR will pop the next data

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501 * status of DMA. This function does not show if the "dma complete"
502 * callback of the DMA transaction has been called. So we prefer
503 * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
504 * same time.
505 */
506 return stm32_port->tx_dma_busy;
507}
508
510static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port)
511{
512 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
513
514 return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT);
515}
516
517static void stm32_usart_tx_dma_complete(void *arg)
518{
519 struct uart_port *port = arg;
520 struct stm32_port *stm32port = to_stm32_port(port);
521 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
522 unsigned long flags;
523
524 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);

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587}
588
589static void stm32_usart_transmit_chars_pio(struct uart_port *port)
590{
591 struct stm32_port *stm32_port = to_stm32_port(port);
592 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
593 struct circ_buf *xmit = &port->state->xmit;
594
509static void stm32_usart_tx_dma_complete(void *arg)
510{
511 struct uart_port *port = arg;
512 struct stm32_port *stm32port = to_stm32_port(port);
513 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
514 unsigned long flags;
515
516 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);

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579}
580
581static void stm32_usart_transmit_chars_pio(struct uart_port *port)
582{
583 struct stm32_port *stm32_port = to_stm32_port(port);
584 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
585 struct circ_buf *xmit = &port->state->xmit;
586
595 if (stm32_usart_tx_dma_enabled(stm32_port))
596 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
597
598 while (!uart_circ_empty(xmit)) {
599 /* Check that TDR is empty before filling FIFO */
600 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
601 break;
602 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
603 uart_xmit_advance(port, 1);
604 }
605

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612
613static void stm32_usart_transmit_chars_dma(struct uart_port *port)
614{
615 struct stm32_port *stm32port = to_stm32_port(port);
616 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
617 struct circ_buf *xmit = &port->state->xmit;
618 struct dma_async_tx_descriptor *desc = NULL;
619 unsigned int count;
587 while (!uart_circ_empty(xmit)) {
588 /* Check that TDR is empty before filling FIFO */
589 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
590 break;
591 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
592 uart_xmit_advance(port, 1);
593 }
594

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601
602static void stm32_usart_transmit_chars_dma(struct uart_port *port)
603{
604 struct stm32_port *stm32port = to_stm32_port(port);
605 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
606 struct circ_buf *xmit = &port->state->xmit;
607 struct dma_async_tx_descriptor *desc = NULL;
608 unsigned int count;
609 int ret;
620
621 if (stm32_usart_tx_dma_started(stm32port)) {
610
611 if (stm32_usart_tx_dma_started(stm32port)) {
622 if (!stm32_usart_tx_dma_enabled(stm32port))
623 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
612 if (dmaengine_tx_status(stm32port->tx_ch,
613 stm32port->tx_ch->cookie,
614 NULL) == DMA_PAUSED) {
615 ret = dmaengine_resume(stm32port->tx_ch);
616 if (ret < 0)
617 goto dma_err;
618 }
624 return;
625 }
626
627 count = uart_circ_chars_pending(xmit);
628
629 if (count > TX_BUF_L)
630 count = TX_BUF_L;
631

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660 * if the callback of the previous is not yet called.
661 */
662 stm32port->tx_dma_busy = true;
663
664 desc->callback = stm32_usart_tx_dma_complete;
665 desc->callback_param = port;
666
667 /* Push current DMA TX transaction in the pending queue */
619 return;
620 }
621
622 count = uart_circ_chars_pending(xmit);
623
624 if (count > TX_BUF_L)
625 count = TX_BUF_L;
626

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655 * if the callback of the previous is not yet called.
656 */
657 stm32port->tx_dma_busy = true;
658
659 desc->callback = stm32_usart_tx_dma_complete;
660 desc->callback_param = port;
661
662 /* Push current DMA TX transaction in the pending queue */
668 if (dma_submit_error(dmaengine_submit(desc))) {
669 /* dma no yet started, safe to free resources */
670 stm32_usart_tx_dma_terminate(stm32port);
671 goto fallback_err;
672 }
663 /* DMA no yet started, safe to free resources */
664 if (dma_submit_error(dmaengine_submit(desc)))
665 goto dma_err;
673
674 /* Issue pending DMA TX requests */
675 dma_async_issue_pending(stm32port->tx_ch);
676
677 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
678
679 uart_xmit_advance(port, count);
680
681 return;
682
666
667 /* Issue pending DMA TX requests */
668 dma_async_issue_pending(stm32port->tx_ch);
669
670 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
671
672 uart_xmit_advance(port, count);
673
674 return;
675
676dma_err:
677 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
678 stm32_usart_tx_dma_terminate(stm32port);
679
683fallback_err:
684 stm32_usart_transmit_chars_pio(port);
685}
686
687static void stm32_usart_transmit_chars(struct uart_port *port)
688{
689 struct stm32_port *stm32_port = to_stm32_port(port);
690 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;

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697 (port->x_char ||
698 !(uart_circ_empty(xmit) || uart_tx_stopped(port)))) {
699 stm32_usart_tc_interrupt_disable(port);
700 stm32_usart_rs485_rts_enable(port);
701 }
702
703 if (port->x_char) {
704 if (stm32_usart_tx_dma_started(stm32_port) &&
680fallback_err:
681 stm32_usart_transmit_chars_pio(port);
682}
683
684static void stm32_usart_transmit_chars(struct uart_port *port)
685{
686 struct stm32_port *stm32_port = to_stm32_port(port);
687 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;

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694 (port->x_char ||
695 !(uart_circ_empty(xmit) || uart_tx_stopped(port)))) {
696 stm32_usart_tc_interrupt_disable(port);
697 stm32_usart_rs485_rts_enable(port);
698 }
699
700 if (port->x_char) {
701 if (stm32_usart_tx_dma_started(stm32_port) &&
705 stm32_usart_tx_dma_enabled(stm32_port))
706 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
707
702 dmaengine_tx_status(stm32_port->tx_ch,
703 stm32_port->tx_ch->cookie,
704 NULL) == DMA_IN_PROGRESS) {
705 ret = dmaengine_pause(stm32_port->tx_ch);
706 if (ret < 0) {
707 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
708 stm32_usart_tx_dma_terminate(stm32_port);
709 }
710 }
708 /* Check that TDR is empty before filling FIFO */
709 ret =
710 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
711 isr,
712 (isr & USART_SR_TXE),
713 10, 1000);
714 if (ret)
715 dev_warn(port->dev, "1 character may be erased\n");
716
717 writel_relaxed(port->x_char, port->membase + ofs->tdr);
718 port->x_char = 0;
719 port->icount.tx++;
711 /* Check that TDR is empty before filling FIFO */
712 ret =
713 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
714 isr,
715 (isr & USART_SR_TXE),
716 10, 1000);
717 if (ret)
718 dev_warn(port->dev, "1 character may be erased\n");
719
720 writel_relaxed(port->x_char, port->membase + ofs->tdr);
721 port->x_char = 0;
722 port->icount.tx++;
720 if (stm32_usart_tx_dma_started(stm32_port))
721 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
723
724 if (stm32_usart_tx_dma_started(stm32_port)) {
725 ret = dmaengine_resume(stm32_port->tx_ch);
726 if (ret < 0) {
727 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
728 stm32_usart_tx_dma_terminate(stm32_port);
729 }
730 }
722 return;
723 }
724
725 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
726 stm32_usart_tx_interrupt_disable(port);
727 return;
728 }
729

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846{
847 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
848}
849
850/* Transmit stop */
851static void stm32_usart_stop_tx(struct uart_port *port)
852{
853 struct stm32_port *stm32_port = to_stm32_port(port);
731 return;
732 }
733
734 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
735 stm32_usart_tx_interrupt_disable(port);
736 return;
737 }
738

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855{
856 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
857}
858
859/* Transmit stop */
860static void stm32_usart_stop_tx(struct uart_port *port)
861{
862 struct stm32_port *stm32_port = to_stm32_port(port);
854 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
863 int ret;
855
856 stm32_usart_tx_interrupt_disable(port);
864
865 stm32_usart_tx_interrupt_disable(port);
857 if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port))
858 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
866 if (stm32_usart_tx_dma_started(stm32_port)) {
867 ret = dmaengine_pause(stm32_port->tx_ch);
868 if (ret < 0) {
869 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
870 stm32_usart_tx_dma_terminate(stm32_port);
871 }
872 }
859
860 stm32_usart_rs485_rts_disable(port);
861}
862
863/* There are probably characters waiting to be transmitted. */
864static void stm32_usart_start_tx(struct uart_port *port)
865{
866 struct circ_buf *xmit = &port->state->xmit;

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874
875 stm32_usart_transmit_chars(port);
876}
877
878/* Flush the transmit buffer. */
879static void stm32_usart_flush_buffer(struct uart_port *port)
880{
881 struct stm32_port *stm32_port = to_stm32_port(port);
873
874 stm32_usart_rs485_rts_disable(port);
875}
876
877/* There are probably characters waiting to be transmitted. */
878static void stm32_usart_start_tx(struct uart_port *port)
879{
880 struct circ_buf *xmit = &port->state->xmit;

--- 7 unchanged lines hidden (view full) ---

888
889 stm32_usart_transmit_chars(port);
890}
891
892/* Flush the transmit buffer. */
893static void stm32_usart_flush_buffer(struct uart_port *port)
894{
895 struct stm32_port *stm32_port = to_stm32_port(port);
882 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
883
896
884 if (stm32_port->tx_ch) {
897 if (stm32_port->tx_ch)
885 stm32_usart_tx_dma_terminate(stm32_port);
898 stm32_usart_tx_dma_terminate(stm32_port);
886 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
887 }
888}
889
890/* Throttle the remote when input buffer is about to overflow. */
891static void stm32_usart_throttle(struct uart_port *port)
892{
893 struct stm32_port *stm32_port = to_stm32_port(port);
894 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
895 unsigned long flags;

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1038static void stm32_usart_shutdown(struct uart_port *port)
1039{
1040 struct stm32_port *stm32_port = to_stm32_port(port);
1041 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1042 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1043 u32 val, isr;
1044 int ret;
1045
899}
900
901/* Throttle the remote when input buffer is about to overflow. */
902static void stm32_usart_throttle(struct uart_port *port)
903{
904 struct stm32_port *stm32_port = to_stm32_port(port);
905 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
906 unsigned long flags;

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1049static void stm32_usart_shutdown(struct uart_port *port)
1050{
1051 struct stm32_port *stm32_port = to_stm32_port(port);
1052 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1053 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1054 u32 val, isr;
1055 int ret;
1056
1046 if (stm32_usart_tx_dma_enabled(stm32_port))
1047 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1048
1049 if (stm32_usart_tx_dma_started(stm32_port))
1050 stm32_usart_tx_dma_terminate(stm32_port);
1051
1057 if (stm32_usart_tx_dma_started(stm32_port))
1058 stm32_usart_tx_dma_terminate(stm32_port);
1059
1060 if (stm32_port->tx_ch)
1061 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1062
1052 /* Disable modem control interrupts */
1053 stm32_usart_disable_ms(port);
1054
1055 val = USART_CR1_TXEIE | USART_CR1_TE;
1056 val |= stm32_port->cr1_irq | USART_CR1_RE;
1057 val |= BIT(cfg->uart_enable_bit);
1058 if (stm32_port->fifoen)
1059 val |= USART_CR1_FIFOEN;

--- 1056 unchanged lines hidden --- 		1063 /* Disable modem control interrupts */
1064 stm32_usart_disable_ms(port);
1065
1066 val = USART_CR1_TXEIE | USART_CR1_TE;
1067 val |= stm32_port->cr1_irq | USART_CR1_RE;
1068 val |= BIT(cfg->uart_enable_bit);
1069 if (stm32_port->fifoen)
1070 val |= USART_CR1_FIFOEN;

--- 1056 unchanged lines hidden ---