serial-tegra.c (447a8b858e4bda41c394b1bc7fdbc9dc0bdf44f6) serial-tegra.c (479e9b94fdce7bc46f669831012fc12f56696fd7)
1/*
2 * serial_tegra.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>

--- 1020 unchanged lines hidden (view full) ---

1029
1030fail_hw_init:
1031 tegra_uart_dma_channel_free(tup, true);
1032fail_rx_dma:
1033 tegra_uart_dma_channel_free(tup, false);
1034 return ret;
1035}
1036
1/*
2 * serial_tegra.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>

--- 1020 unchanged lines hidden (view full) ---

1029
1030fail_hw_init:
1031 tegra_uart_dma_channel_free(tup, true);
1032fail_rx_dma:
1033 tegra_uart_dma_channel_free(tup, false);
1034 return ret;
1035}
1036
1037/*
1038 * Flush any TX data submitted for DMA and PIO. Called when the
1039 * TX circular buffer is reset.
1040 */
1041static void tegra_uart_flush_buffer(struct uart_port *u)
1042{
1043 struct tegra_uart_port *tup = to_tegra_uport(u);
1044
1045 tup->tx_bytes = 0;
1046 if (tup->tx_dma_chan)
1047 dmaengine_terminate_all(tup->tx_dma_chan);
1048 return;
1049}
1050
1037static void tegra_uart_shutdown(struct uart_port *u)
1038{
1039 struct tegra_uart_port *tup = to_tegra_uport(u);
1040
1041 tegra_uart_hw_deinit(tup);
1042
1043 tup->rx_in_progress = 0;
1044 tup->tx_in_progress = 0;
1045
1046 tegra_uart_dma_channel_free(tup, true);
1047 tegra_uart_dma_channel_free(tup, false);
1048 free_irq(u->irq, tup);
1051static void tegra_uart_shutdown(struct uart_port *u)
1052{
1053 struct tegra_uart_port *tup = to_tegra_uport(u);
1054
1055 tegra_uart_hw_deinit(tup);
1056
1057 tup->rx_in_progress = 0;
1058 tup->tx_in_progress = 0;
1059
1060 tegra_uart_dma_channel_free(tup, true);
1061 tegra_uart_dma_channel_free(tup, false);
1062 free_irq(u->irq, tup);
1063
1064 tegra_uart_flush_buffer(u);
1049}
1050
1051static void tegra_uart_enable_ms(struct uart_port *u)
1052{
1053 struct tegra_uart_port *tup = to_tegra_uport(u);
1054
1055 if (tup->enable_modem_interrupt) {
1056 tup->ier_shadow |= UART_IER_MSI;

--- 112 unchanged lines hidden (view full) ---

1169 /* Reenable interrupt */
1170 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1171 tegra_uart_read(tup, UART_IER);
1172
1173 spin_unlock_irqrestore(&u->lock, flags);
1174 return;
1175}
1176
1065}
1066
1067static void tegra_uart_enable_ms(struct uart_port *u)
1068{
1069 struct tegra_uart_port *tup = to_tegra_uport(u);
1070
1071 if (tup->enable_modem_interrupt) {
1072 tup->ier_shadow |= UART_IER_MSI;

--- 112 unchanged lines hidden (view full) ---

1185 /* Reenable interrupt */
1186 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1187 tegra_uart_read(tup, UART_IER);
1188
1189 spin_unlock_irqrestore(&u->lock, flags);
1190 return;
1191}
1192
1177/*
1178 * Flush any TX data submitted for DMA and PIO. Called when the
1179 * TX circular buffer is reset.
1180 */
1181static void tegra_uart_flush_buffer(struct uart_port *u)
1182{
1183 struct tegra_uart_port *tup = to_tegra_uport(u);
1184
1185 tup->tx_bytes = 0;
1186 if (tup->tx_dma_chan)
1187 dmaengine_terminate_all(tup->tx_dma_chan);
1188 return;
1189}
1190
1191static const char *tegra_uart_type(struct uart_port *u)
1192{
1193 return TEGRA_UART_TYPE;
1194}
1195
1196static struct uart_ops tegra_uart_ops = {
1197 .tx_empty = tegra_uart_tx_empty,
1198 .set_mctrl = tegra_uart_set_mctrl,

--- 208 unchanged lines hidden --- 		1193static const char *tegra_uart_type(struct uart_port *u)
1194{
1195 return TEGRA_UART_TYPE;
1196}
1197
1198static struct uart_ops tegra_uart_ops = {
1199 .tx_empty = tegra_uart_tx_empty,
1200 .set_mctrl = tegra_uart_set_mctrl,

--- 208 unchanged lines hidden ---