omap-serial.c (0fdc50dfab47d525b71a9f0d8310746cdc0c09c5) omap-serial.c (c150c0f362c1e51c0e3216c9912b85b71d00e70d)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:

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28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/serial_core.h>
31#include <linux/irq.h>
32#include <linux/pm_runtime.h>
33#include <linux/pm_wakeirq.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:

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28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/serial_core.h>
31#include <linux/irq.h>
32#include <linux/pm_runtime.h>
33#include <linux/pm_wakeirq.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/gpio.h>
37#include <linux/of_gpio.h>
36#include <linux/gpio/consumer.h>
38#include <linux/platform_data/serial-omap.h>
39
37#include <linux/platform_data/serial-omap.h>
38
40#include <dt-bindings/gpio/gpio.h>
41
42#define OMAP_MAX_HSUART_PORTS 10
43
44#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
45
46#define OMAP_UART_REV_42 0x0402
47#define OMAP_UART_REV_46 0x0406
48#define OMAP_UART_REV_52 0x0502
49#define OMAP_UART_REV_63 0x0603

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150 unsigned int lsr_break_flag;
151 unsigned char msr_saved_flags;
152 char name[20];
153 unsigned long port_activity;
154 int context_loss_cnt;
155 u32 errata;
156 u32 features;
157
39#define OMAP_MAX_HSUART_PORTS 10
40
41#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
42
43#define OMAP_UART_REV_42 0x0402
44#define OMAP_UART_REV_46 0x0406
45#define OMAP_UART_REV_52 0x0502
46#define OMAP_UART_REV_63 0x0603

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147 unsigned int lsr_break_flag;
148 unsigned char msr_saved_flags;
149 char name[20];
150 unsigned long port_activity;
151 int context_loss_cnt;
152 u32 errata;
153 u32 features;
154
158 int rts_gpio;
155 struct gpio_desc *rts_gpiod;
159
160 struct pm_qos_request pm_qos_request;
161 u32 latency;
162 u32 calc_latency;
163 struct work_struct qos_work;
164 bool is_suspending;
165};
166

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300 * is fired when TX FIFO is below the trigger level,
301 * disable THR interrupts and toggle the RS-485 GPIO
302 * data direction pin if needed.
303 */
304 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
305 serial_out(up, UART_OMAP_SCR, up->scr);
306 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
307 1 : 0;
156
157 struct pm_qos_request pm_qos_request;
158 u32 latency;
159 u32 calc_latency;
160 struct work_struct qos_work;
161 bool is_suspending;
162};
163

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297 * is fired when TX FIFO is below the trigger level,
298 * disable THR interrupts and toggle the RS-485 GPIO
299 * data direction pin if needed.
300 */
301 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
302 serial_out(up, UART_OMAP_SCR, up->scr);
303 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
304 1 : 0;
308 if (gpio_get_value(up->rts_gpio) != res) {
305 if (gpiod_get_value(up->rts_gpiod) != res) {
309 if (port->rs485.delay_rts_after_send > 0)
310 mdelay(
311 port->rs485.delay_rts_after_send);
306 if (port->rs485.delay_rts_after_send > 0)
307 mdelay(
308 port->rs485.delay_rts_after_send);
312 gpio_set_value(up->rts_gpio, res);
309 gpiod_set_value(up->rts_gpiod, res);
313 }
314 } else {
315 /* We're asked to stop, but there's still stuff in the
316 * UART FIFO, so make sure the THR interrupt is fired
317 * when both TX FIFO and TX shift register are empty.
318 * The next THR interrupt (if no transmission is started
319 * in the meantime) will indicate the end of a
320 * transmission. Therefore we _don't_ disable THR

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409 /* Handle RS-485 */
410 if (port->rs485.flags & SER_RS485_ENABLED) {
411 /* Fire THR interrupts when FIFO is below trigger level */
412 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
413 serial_out(up, UART_OMAP_SCR, up->scr);
414
415 /* if rts not already enabled */
416 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
310 }
311 } else {
312 /* We're asked to stop, but there's still stuff in the
313 * UART FIFO, so make sure the THR interrupt is fired
314 * when both TX FIFO and TX shift register are empty.
315 * The next THR interrupt (if no transmission is started
316 * in the meantime) will indicate the end of a
317 * transmission. Therefore we _don't_ disable THR

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406 /* Handle RS-485 */
407 if (port->rs485.flags & SER_RS485_ENABLED) {
408 /* Fire THR interrupts when FIFO is below trigger level */
409 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
410 serial_out(up, UART_OMAP_SCR, up->scr);
411
412 /* if rts not already enabled */
413 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
417 if (gpio_get_value(up->rts_gpio) != res) {
418 gpio_set_value(up->rts_gpio, res);
414 if (gpiod_get_value(up->rts_gpiod) != res) {
415 gpiod_set_value(up->rts_gpiod, res);
419 if (port->rs485.delay_rts_before_send > 0)
420 mdelay(port->rs485.delay_rts_before_send);
421 }
422 }
423
424 if ((port->rs485.flags & SER_RS485_ENABLED) &&
425 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
426 serial_omap_stop_rx(port);

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826 dev_pm_clear_wake_irq(up->dev);
827}
828
829static void serial_omap_uart_qos_work(struct work_struct *work)
830{
831 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
832 qos_work);
833
416 if (port->rs485.delay_rts_before_send > 0)
417 mdelay(port->rs485.delay_rts_before_send);
418 }
419 }
420
421 if ((port->rs485.flags & SER_RS485_ENABLED) &&
422 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
423 serial_omap_stop_rx(port);

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823 dev_pm_clear_wake_irq(up->dev);
824}
825
826static void serial_omap_uart_qos_work(struct work_struct *work)
827{
828 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
829 qos_work);
830
834 pm_qos_update_request(&up->pm_qos_request, up->latency);
831 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
835}
836
837static void
838serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
839 struct ktermios *old)
840{
841 struct uart_omap_port *up = to_uart_omap_port(port);
842 unsigned char cval = 0;

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1411
1412 /* store new config */
1413 port->rs485 = *rs485;
1414
1415 /*
1416 * Just as a precaution, only allow rs485
1417 * to be enabled if the gpio pin is valid
1418 */
832}
833
834static void
835serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
836 struct ktermios *old)
837{
838 struct uart_omap_port *up = to_uart_omap_port(port);
839 unsigned char cval = 0;

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1408
1409 /* store new config */
1410 port->rs485 = *rs485;
1411
1412 /*
1413 * Just as a precaution, only allow rs485
1414 * to be enabled if the gpio pin is valid
1415 */
1419 if (gpio_is_valid(up->rts_gpio)) {
1416 if (up->rts_gpiod) {
1420 /* enable / disable rts */
1421 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1422 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1423 val = (port->rs485.flags & val) ? 1 : 0;
1417 /* enable / disable rts */
1418 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1419 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1420 val = (port->rs485.flags & val) ? 1 : 0;
1424 gpio_set_value(up->rts_gpio, val);
1421 gpiod_set_value(up->rts_gpiod, val);
1425 } else
1426 port->rs485.flags &= ~SER_RS485_ENABLED;
1427
1428 /* Enable interrupts */
1429 up->ier = mode;
1430 serial_out(up, UART_IER, up->ier);
1431
1432 /* If RS-485 is disabled, make sure the THR interrupt is fired when

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1593 &omap_up_info->uartclk);
1594
1595 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1596
1597 return omap_up_info;
1598}
1599
1600static int serial_omap_probe_rs485(struct uart_omap_port *up,
1422 } else
1423 port->rs485.flags &= ~SER_RS485_ENABLED;
1424
1425 /* Enable interrupts */
1426 up->ier = mode;
1427 serial_out(up, UART_IER, up->ier);
1428
1429 /* If RS-485 is disabled, make sure the THR interrupt is fired when

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1590 &omap_up_info->uartclk);
1591
1592 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1593
1594 return omap_up_info;
1595}
1596
1597static int serial_omap_probe_rs485(struct uart_omap_port *up,
1601 struct device_node *np)
1598 struct device *dev)
1602{
1603 struct serial_rs485 *rs485conf = &up->port.rs485;
1599{
1600 struct serial_rs485 *rs485conf = &up->port.rs485;
1601 struct device_node *np = dev->of_node;
1602 enum gpiod_flags gflags;
1604 int ret;
1605
1606 rs485conf->flags = 0;
1603 int ret;
1604
1605 rs485conf->flags = 0;
1607 up->rts_gpio = -EINVAL;
1606 up->rts_gpiod = NULL;
1608
1609 if (!np)
1610 return 0;
1611
1607
1608 if (!np)
1609 return 0;
1610
1612 uart_get_rs485_mode(up->dev, rs485conf);
1611 ret = uart_get_rs485_mode(&up->port);
1612 if (ret)
1613 return ret;
1613
1614 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1615 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1616 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1617 } else {
1618 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1619 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1620 }
1621
1622 /* check for tx enable gpio */
1614
1615 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1616 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1617 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1618 } else {
1619 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1620 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1621 }
1622
1623 /* check for tx enable gpio */
1623 up->rts_gpio = of_get_named_gpio(np, "rts-gpio", 0);
1624 if (gpio_is_valid(up->rts_gpio)) {
1625 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1626 if (ret < 0)
1624 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1625 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1626 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1627 if (IS_ERR(up->rts_gpiod)) {
1628 ret = PTR_ERR(up->rts_gpiod);
1629 if (ret == -EPROBE_DEFER)
1627 return ret;
1630 return ret;
1628 ret = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0;
1629 ret = gpio_direction_output(up->rts_gpio, ret);
1630 if (ret < 0)
1631 return ret;
1632 } else if (up->rts_gpio == -EPROBE_DEFER) {
1633 return -EPROBE_DEFER;
1631 /*
1632 * FIXME: the code historically ignored any other error than
1633 * -EPROBE_DEFER and just went on without GPIO.
1634 */
1635 up->rts_gpiod = NULL;
1634 } else {
1636 } else {
1635 up->rts_gpio = -EINVAL;
1637 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1636 }
1637
1638 return 0;
1639}
1640
1641static int serial_omap_probe(struct platform_device *pdev)
1642{
1643 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);

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1700 goto err_port_line;
1701 }
1702
1703 up->wakeirq = wakeirq;
1704 if (!up->wakeirq)
1705 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1706 up->port.line);
1707
1638 }
1639
1640 return 0;
1641}
1642
1643static int serial_omap_probe(struct platform_device *pdev)
1644{
1645 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);

--- 56 unchanged lines hidden (view full) ---

1702 goto err_port_line;
1703 }
1704
1705 up->wakeirq = wakeirq;
1706 if (!up->wakeirq)
1707 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1708 up->port.line);
1709
1708 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1710 ret = serial_omap_probe_rs485(up, &pdev->dev);
1709 if (ret < 0)
1710 goto err_rs485;
1711
1712 sprintf(up->name, "OMAP UART%d", up->port.line);
1713 up->port.mapbase = mem->start;
1714 up->port.membase = base;
1715 up->port.flags = omap_up_info->flags;
1716 up->port.uartclk = omap_up_info->uartclk;
1717 up->port.rs485_config = serial_omap_config_rs485;
1718 if (!up->port.uartclk) {
1719 up->port.uartclk = DEFAULT_CLK_SPEED;
1720 dev_warn(&pdev->dev,
1721 "No clock speed specified: using default: %d\n",
1722 DEFAULT_CLK_SPEED);
1723 }
1724
1711 if (ret < 0)
1712 goto err_rs485;
1713
1714 sprintf(up->name, "OMAP UART%d", up->port.line);
1715 up->port.mapbase = mem->start;
1716 up->port.membase = base;
1717 up->port.flags = omap_up_info->flags;
1718 up->port.uartclk = omap_up_info->uartclk;
1719 up->port.rs485_config = serial_omap_config_rs485;
1720 if (!up->port.uartclk) {
1721 up->port.uartclk = DEFAULT_CLK_SPEED;
1722 dev_warn(&pdev->dev,
1723 "No clock speed specified: using default: %d\n",
1724 DEFAULT_CLK_SPEED);
1725 }
1726
1725 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1726 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1727 pm_qos_add_request(&up->pm_qos_request,
1728 PM_QOS_CPU_DMA_LATENCY, up->latency);
1727 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1728 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1729 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1729 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1730
1731 platform_set_drvdata(pdev, up);
1732 if (omap_up_info->autosuspend_timeout == 0)
1733 omap_up_info->autosuspend_timeout = -1;
1734
1735 device_init_wakeup(up->dev, true);
1736 pm_runtime_use_autosuspend(&pdev->dev);

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1754 pm_runtime_mark_last_busy(up->dev);
1755 pm_runtime_put_autosuspend(up->dev);
1756 return 0;
1757
1758err_add_port:
1759 pm_runtime_dont_use_autosuspend(&pdev->dev);
1760 pm_runtime_put_sync(&pdev->dev);
1761 pm_runtime_disable(&pdev->dev);
1730 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1731
1732 platform_set_drvdata(pdev, up);
1733 if (omap_up_info->autosuspend_timeout == 0)
1734 omap_up_info->autosuspend_timeout = -1;
1735
1736 device_init_wakeup(up->dev, true);
1737 pm_runtime_use_autosuspend(&pdev->dev);

--- 17 unchanged lines hidden (view full) ---

1755 pm_runtime_mark_last_busy(up->dev);
1756 pm_runtime_put_autosuspend(up->dev);
1757 return 0;
1758
1759err_add_port:
1760 pm_runtime_dont_use_autosuspend(&pdev->dev);
1761 pm_runtime_put_sync(&pdev->dev);
1762 pm_runtime_disable(&pdev->dev);
1762 pm_qos_remove_request(&up->pm_qos_request);
1763 cpu_latency_qos_remove_request(&up->pm_qos_request);
1763 device_init_wakeup(up->dev, false);
1764err_rs485:
1765err_port_line:
1766 return ret;
1767}
1768
1769static int serial_omap_remove(struct platform_device *dev)
1770{
1771 struct uart_omap_port *up = platform_get_drvdata(dev);
1772
1773 pm_runtime_get_sync(up->dev);
1774
1775 uart_remove_one_port(&serial_omap_reg, &up->port);
1776
1777 pm_runtime_dont_use_autosuspend(up->dev);
1778 pm_runtime_put_sync(up->dev);
1779 pm_runtime_disable(up->dev);
1764 device_init_wakeup(up->dev, false);
1765err_rs485:
1766err_port_line:
1767 return ret;
1768}
1769
1770static int serial_omap_remove(struct platform_device *dev)
1771{
1772 struct uart_omap_port *up = platform_get_drvdata(dev);
1773
1774 pm_runtime_get_sync(up->dev);
1775
1776 uart_remove_one_port(&serial_omap_reg, &up->port);
1777
1778 pm_runtime_dont_use_autosuspend(up->dev);
1779 pm_runtime_put_sync(up->dev);
1780 pm_runtime_disable(up->dev);
1780 pm_qos_remove_request(&up->pm_qos_request);
1781 cpu_latency_qos_remove_request(&up->pm_qos_request);
1781 device_init_wakeup(&dev->dev, false);
1782
1783 return 0;
1784}
1785
1786/*
1787 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1788 * The access to uart register after MDR1 Access

--- 75 unchanged lines hidden (view full) ---

1864 if (up->is_suspending && !console_suspend_enabled &&
1865 uart_console(&up->port))
1866 return -EBUSY;
1867
1868 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1869
1870 serial_omap_enable_wakeup(up, true);
1871
1782 device_init_wakeup(&dev->dev, false);
1783
1784 return 0;
1785}
1786
1787/*
1788 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1789 * The access to uart register after MDR1 Access

--- 75 unchanged lines hidden (view full) ---

1865 if (up->is_suspending && !console_suspend_enabled &&
1866 uart_console(&up->port))
1867 return -EBUSY;
1868
1869 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1870
1871 serial_omap_enable_wakeup(up, true);
1872
1872 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1873 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1873 schedule_work(&up->qos_work);
1874
1875 return 0;
1876}
1877
1878static int serial_omap_runtime_resume(struct device *dev)
1879{
1880 struct uart_omap_port *up = dev_get_drvdata(dev);

--- 72 unchanged lines hidden --- 		1874 schedule_work(&up->qos_work);
1875
1876 return 0;
1877}
1878
1879static int serial_omap_runtime_resume(struct device *dev)
1880{
1881 struct uart_omap_port *up = dev_get_drvdata(dev);

--- 72 unchanged lines hidden ---