amba-pl011.c (3f60db4bde17088feed5f143582d7661cdbb9a01) amba-pl011.c (258aea76f552cc755da92e7e823abbb85e021514)
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA

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46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
48#include <linux/clk.h>
49#include <linux/slab.h>
50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
53#include <linux/delay.h>
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA

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46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
48#include <linux/clk.h>
49#include <linux/slab.h>
50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
53#include <linux/delay.h>
54#include <linux/types.h>
54
55#include <asm/io.h>
56#include <asm/sizes.h>
57
58#define UART_NR 14
59
60#define SERIAL_AMBA_MAJOR 204
61#define SERIAL_AMBA_MINOR 64

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154 struct clk *clk;
155 const struct vendor_data *vendor;
156 unsigned int dmacr; /* dma control reg */
157 unsigned int im; /* interrupt mask */
158 unsigned int old_status;
159 unsigned int fifosize; /* vendor-specific */
160 unsigned int lcrh_tx; /* vendor-specific */
161 unsigned int lcrh_rx; /* vendor-specific */
55
56#include <asm/io.h>
57#include <asm/sizes.h>
58
59#define UART_NR 14
60
61#define SERIAL_AMBA_MAJOR 204
62#define SERIAL_AMBA_MINOR 64

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155 struct clk *clk;
156 const struct vendor_data *vendor;
157 unsigned int dmacr; /* dma control reg */
158 unsigned int im; /* interrupt mask */
159 unsigned int old_status;
160 unsigned int fifosize; /* vendor-specific */
161 unsigned int lcrh_tx; /* vendor-specific */
162 unsigned int lcrh_rx; /* vendor-specific */
162 unsigned int old_cr; /* state during shutdown */
163 bool autorts;
164 char type[12];
165 bool interrupt_may_hang; /* vendor-specific */
166#ifdef CONFIG_DMA_ENGINE
167 /* DMA stuff */
168 bool using_tx_dma;
169 bool using_rx_dma;
170 struct pl011_dmarx_data dmarx;

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266{
267 /* DMA is the sole user of the platform data right now */
268 struct amba_pl011_data *plat = uap->port.dev->platform_data;
269 struct dma_slave_config tx_conf = {
270 .dst_addr = uap->port.mapbase + UART01x_DR,
271 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
272 .direction = DMA_MEM_TO_DEV,
273 .dst_maxburst = uap->fifosize >> 1,
163 bool autorts;
164 char type[12];
165 bool interrupt_may_hang; /* vendor-specific */
166#ifdef CONFIG_DMA_ENGINE
167 /* DMA stuff */
168 bool using_tx_dma;
169 bool using_rx_dma;
170 struct pl011_dmarx_data dmarx;

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266{
267 /* DMA is the sole user of the platform data right now */
268 struct amba_pl011_data *plat = uap->port.dev->platform_data;
269 struct dma_slave_config tx_conf = {
270 .dst_addr = uap->port.mapbase + UART01x_DR,
271 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
272 .direction = DMA_MEM_TO_DEV,
273 .dst_maxburst = uap->fifosize >> 1,
274 .device_fc = false,
274 };
275 struct dma_chan *chan;
276 dma_cap_mask_t mask;
277
278 /* We need platform data */
279 if (!plat || !plat->dma_filter) {
280 dev_info(uap->port.dev, "no DMA platform data\n");
281 return;

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299
300 /* Optionally make use of an RX channel as well */
301 if (plat->dma_rx_param) {
302 struct dma_slave_config rx_conf = {
303 .src_addr = uap->port.mapbase + UART01x_DR,
304 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
305 .direction = DMA_DEV_TO_MEM,
306 .src_maxburst = uap->fifosize >> 1,
275 };
276 struct dma_chan *chan;
277 dma_cap_mask_t mask;
278
279 /* We need platform data */
280 if (!plat || !plat->dma_filter) {
281 dev_info(uap->port.dev, "no DMA platform data\n");
282 return;

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300
301 /* Optionally make use of an RX channel as well */
302 if (plat->dma_rx_param) {
303 struct dma_slave_config rx_conf = {
304 .src_addr = uap->port.mapbase + UART01x_DR,
305 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
306 .direction = DMA_DEV_TO_MEM,
307 .src_maxburst = uap->fifosize >> 1,
308 .device_fc = false,
307 };
308
309 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
310 if (!chan) {
311 dev_err(uap->port.dev, "no RX DMA channel!\n");
312 return;
313 }
314

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1407 for (i = 0; i < 10; ++i)
1408 writew(0xff, uap->port.membase + UART011_MIS);
1409 writew(0, uap->port.membase + uap->lcrh_tx);
1410 }
1411 writew(0, uap->port.membase + UART01x_DR);
1412 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1413 barrier();
1414
309 };
310
311 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
312 if (!chan) {
313 dev_err(uap->port.dev, "no RX DMA channel!\n");
314 return;
315 }
316

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1409 for (i = 0; i < 10; ++i)
1410 writew(0xff, uap->port.membase + UART011_MIS);
1411 writew(0, uap->port.membase + uap->lcrh_tx);
1412 }
1413 writew(0, uap->port.membase + UART01x_DR);
1414 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1415 barrier();
1416
1415 /* restore RTS and DTR */
1416 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1417 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1417 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1418 writew(cr, uap->port.membase + UART011_CR);
1419
1420 /* Clear pending error interrupts */
1421 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
1422 uap->port.membase + UART011_ICR);
1423
1424 /*
1425 * initialise the old status of the modem signals

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1467 val = readw(uap->port.membase + lcrh);
1468 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1469 writew(val, uap->port.membase + lcrh);
1470}
1471
1472static void pl011_shutdown(struct uart_port *port)
1473{
1474 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1418 writew(cr, uap->port.membase + UART011_CR);
1419
1420 /* Clear pending error interrupts */
1421 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
1422 uap->port.membase + UART011_ICR);
1423
1424 /*
1425 * initialise the old status of the modem signals

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1467 val = readw(uap->port.membase + lcrh);
1468 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1469 writew(val, uap->port.membase + lcrh);
1470}
1471
1472static void pl011_shutdown(struct uart_port *port)
1473{
1474 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1475 unsigned int cr;
1476
1477 /*
1478 * disable all interrupts
1479 */
1480 spin_lock_irq(&uap->port.lock);
1481 uap->im = 0;
1482 writew(uap->im, uap->port.membase + UART011_IMSC);
1483 writew(0xffff, uap->port.membase + UART011_ICR);
1484 spin_unlock_irq(&uap->port.lock);
1485
1486 pl011_dma_shutdown(uap);
1487
1488 /*
1489 * Free the interrupt
1490 */
1491 free_irq(uap->port.irq, uap);
1492
1493 /*
1494 * disable the port
1475
1476 /*
1477 * disable all interrupts
1478 */
1479 spin_lock_irq(&uap->port.lock);
1480 uap->im = 0;
1481 writew(uap->im, uap->port.membase + UART011_IMSC);
1482 writew(0xffff, uap->port.membase + UART011_ICR);
1483 spin_unlock_irq(&uap->port.lock);
1484
1485 pl011_dma_shutdown(uap);
1486
1487 /*
1488 * Free the interrupt
1489 */
1490 free_irq(uap->port.irq, uap);
1491
1492 /*
1493 * disable the port
1495 * disable the port. It should not disable RTS and DTR.
1496 * Also RTS and DTR state should be preserved to restore
1497 * it during startup().
1498 */
1499 uap->autorts = false;
1494 */
1495 uap->autorts = false;
1500 cr = readw(uap->port.membase + UART011_CR);
1501 uap->old_cr = cr;
1502 cr &= UART011_CR_RTS | UART011_CR_DTR;
1503 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1504 writew(cr, uap->port.membase + UART011_CR);
1496 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
1505
1506 /*
1507 * disable break condition and fifos
1508 */
1509 pl011_shutdown_channel(uap, uap->lcrh_rx);
1510 if (uap->lcrh_rx != uap->lcrh_tx)
1511 pl011_shutdown_channel(uap, uap->lcrh_tx);
1512

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1746 writew(ch, uap->port.membase + UART01x_DR);
1747}
1748
1749static void
1750pl011_console_write(struct console *co, const char *s, unsigned int count)
1751{
1752 struct uart_amba_port *uap = amba_ports[co->index];
1753 unsigned int status, old_cr, new_cr;
1497
1498 /*
1499 * disable break condition and fifos
1500 */
1501 pl011_shutdown_channel(uap, uap->lcrh_rx);
1502 if (uap->lcrh_rx != uap->lcrh_tx)
1503 pl011_shutdown_channel(uap, uap->lcrh_tx);
1504

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1738 writew(ch, uap->port.membase + UART01x_DR);
1739}
1740
1741static void
1742pl011_console_write(struct console *co, const char *s, unsigned int count)
1743{
1744 struct uart_amba_port *uap = amba_ports[co->index];
1745 unsigned int status, old_cr, new_cr;
1754 unsigned long flags;
1755 int locked = 1;
1756
1757 clk_enable(uap->clk);
1758
1746
1747 clk_enable(uap->clk);
1748
1759 local_irq_save(flags);
1760 if (uap->port.sysrq)
1761 locked = 0;
1762 else if (oops_in_progress)
1763 locked = spin_trylock(&uap->port.lock);
1764 else
1765 spin_lock(&uap->port.lock);
1766
1767 /*
1768 * First save the CR then disable the interrupts
1769 */
1770 old_cr = readw(uap->port.membase + UART011_CR);
1771 new_cr = old_cr & ~UART011_CR_CTSEN;
1772 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1773 writew(new_cr, uap->port.membase + UART011_CR);
1774
1775 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1776
1777 /*
1778 * Finally, wait for transmitter to become empty
1779 * and restore the TCR
1780 */
1781 do {
1782 status = readw(uap->port.membase + UART01x_FR);
1783 } while (status & UART01x_FR_BUSY);
1784 writew(old_cr, uap->port.membase + UART011_CR);
1785
1749 /*
1750 * First save the CR then disable the interrupts
1751 */
1752 old_cr = readw(uap->port.membase + UART011_CR);
1753 new_cr = old_cr & ~UART011_CR_CTSEN;
1754 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1755 writew(new_cr, uap->port.membase + UART011_CR);
1756
1757 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1758
1759 /*
1760 * Finally, wait for transmitter to become empty
1761 * and restore the TCR
1762 */
1763 do {
1764 status = readw(uap->port.membase + UART01x_FR);
1765 } while (status & UART01x_FR_BUSY);
1766 writew(old_cr, uap->port.membase + UART011_CR);
1767
1786 if (locked)
1787 spin_unlock(&uap->port.lock);
1788 local_irq_restore(flags);
1789
1790 clk_disable(uap->clk);
1791}
1792
1793static void __init
1794pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1795 int *parity, int *bits)
1796{
1797 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {

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1925 if (IS_ERR(uap->clk)) {
1926 ret = PTR_ERR(uap->clk);
1927 goto unmap;
1928 }
1929
1930 uap->vendor = vendor;
1931 uap->lcrh_rx = vendor->lcrh_rx;
1932 uap->lcrh_tx = vendor->lcrh_tx;
1768 clk_disable(uap->clk);
1769}
1770
1771static void __init
1772pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1773 int *parity, int *bits)
1774{
1775 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {

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1903 if (IS_ERR(uap->clk)) {
1904 ret = PTR_ERR(uap->clk);
1905 goto unmap;
1906 }
1907
1908 uap->vendor = vendor;
1909 uap->lcrh_rx = vendor->lcrh_rx;
1910 uap->lcrh_tx = vendor->lcrh_tx;
1933 uap->old_cr = 0;
1934 uap->fifosize = vendor->fifosize;
1935 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1936 uap->port.dev = &dev->dev;
1937 uap->port.mapbase = dev->res.start;
1938 uap->port.membase = base;
1939 uap->port.iotype = UPIO_MEM;
1940 uap->port.irq = dev->irq[0];
1941 uap->port.fifosize = uap->fifosize;

--- 126 unchanged lines hidden --- 		1911 uap->fifosize = vendor->fifosize;
1912 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1913 uap->port.dev = &dev->dev;
1914 uap->port.mapbase = dev->res.start;
1915 uap->port.membase = base;
1916 uap->port.iotype = UPIO_MEM;
1917 uap->port.irq = dev->irq[0];
1918 uap->port.fifosize = uap->fifosize;

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