| tb_regs.h (341d45188a7800ae3bc18558d62020787b78397e) | tb_regs.h (b2911a593a705e54adde6d06d4657c1ff2f16583) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Thunderbolt driver - Port/Switch config area registers 4 * 5 * Every thunderbolt device consists (logically) of a switch with multiple 6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH, 7 * COUNTERS) which are used to configure the device. 8 * --- 164 unchanged lines hidden (view full) --- 173 174/* USB4 version 1.0 */ 175#define USB4_VERSION_1_0 0x20 176 177#define ROUTER_CS_1 0x01 178#define ROUTER_CS_4 0x04 179#define ROUTER_CS_5 0x05 180#define ROUTER_CS_5_SLP BIT(0) | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Thunderbolt driver - Port/Switch config area registers 4 * 5 * Every thunderbolt device consists (logically) of a switch with multiple 6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH, 7 * COUNTERS) which are used to configure the device. 8 * --- 164 unchanged lines hidden (view full) --- 173 174/* USB4 version 1.0 */ 175#define USB4_VERSION_1_0 0x20 176 177#define ROUTER_CS_1 0x01 178#define ROUTER_CS_4 0x04 179#define ROUTER_CS_5 0x05 180#define ROUTER_CS_5_SLP BIT(0) |
| 181#define ROUTER_CS_5_WOP BIT(1) 182#define ROUTER_CS_5_WOU BIT(2) |
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| 181#define ROUTER_CS_5_C3S BIT(23) 182#define ROUTER_CS_5_PTO BIT(24) 183#define ROUTER_CS_5_UTO BIT(25) 184#define ROUTER_CS_5_HCO BIT(26) 185#define ROUTER_CS_5_CV BIT(31) 186#define ROUTER_CS_6 0x06 187#define ROUTER_CS_6_SLPR BIT(0) 188#define ROUTER_CS_6_TNS BIT(1) | 183#define ROUTER_CS_5_C3S BIT(23) 184#define ROUTER_CS_5_PTO BIT(24) 185#define ROUTER_CS_5_UTO BIT(25) 186#define ROUTER_CS_5_HCO BIT(26) 187#define ROUTER_CS_5_CV BIT(31) 188#define ROUTER_CS_6 0x06 189#define ROUTER_CS_6_SLPR BIT(0) 190#define ROUTER_CS_6_TNS BIT(1) |
| 191#define ROUTER_CS_6_WOPS BIT(2) 192#define ROUTER_CS_6_WOUS BIT(3) |
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| 189#define ROUTER_CS_6_HCI BIT(18) 190#define ROUTER_CS_6_CR BIT(25) 191#define ROUTER_CS_7 0x07 192#define ROUTER_CS_9 0x09 193#define ROUTER_CS_25 0x19 194#define ROUTER_CS_26 0x1a 195#define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24) 196#define ROUTER_CS_26_STATUS_SHIFT 24 --- 100 unchanged lines hidden (view full) --- 297#define PORT_CS_1_WNR_WRITE BIT(24) 298#define PORT_CS_1_NR BIT(25) 299#define PORT_CS_1_RC BIT(26) 300#define PORT_CS_1_PND BIT(31) 301#define PORT_CS_2 0x02 302#define PORT_CS_18 0x12 303#define PORT_CS_18_BE BIT(8) 304#define PORT_CS_18_TCM BIT(9) | 193#define ROUTER_CS_6_HCI BIT(18) 194#define ROUTER_CS_6_CR BIT(25) 195#define ROUTER_CS_7 0x07 196#define ROUTER_CS_9 0x09 197#define ROUTER_CS_25 0x19 198#define ROUTER_CS_26 0x1a 199#define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24) 200#define ROUTER_CS_26_STATUS_SHIFT 24 --- 100 unchanged lines hidden (view full) --- 301#define PORT_CS_1_WNR_WRITE BIT(24) 302#define PORT_CS_1_NR BIT(25) 303#define PORT_CS_1_RC BIT(26) 304#define PORT_CS_1_PND BIT(31) 305#define PORT_CS_2 0x02 306#define PORT_CS_18 0x12 307#define PORT_CS_18_BE BIT(8) 308#define PORT_CS_18_TCM BIT(9) |
| 309#define PORT_CS_18_WOU4S BIT(18) |
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| 305#define PORT_CS_19 0x13 306#define PORT_CS_19_PC BIT(3) 307#define PORT_CS_19_PID BIT(4) | 310#define PORT_CS_19 0x13 311#define PORT_CS_19_PC BIT(3) 312#define PORT_CS_19_PID BIT(4) |
| 313#define PORT_CS_19_WOC BIT(16) 314#define PORT_CS_19_WOD BIT(17) 315#define PORT_CS_19_WOU4 BIT(18) |
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| 308 309/* Display Port adapter registers */ 310#define ADP_DP_CS_0 0x00 311#define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16) 312#define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16 313#define ADP_DP_CS_0_AE BIT(30) 314#define ADP_DP_CS_0_VE BIT(31) 315#define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0) --- 97 unchanged lines hidden (view full) --- 413#define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1 414#define TB_LC_POWER 0x740 415 416/* Link controller registers */ 417#define TB_LC_PORT_ATTR 0x8d 418#define TB_LC_PORT_ATTR_BE BIT(12) 419 420#define TB_LC_SX_CTRL 0x96 | 316 317/* Display Port adapter registers */ 318#define ADP_DP_CS_0 0x00 319#define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16) 320#define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16 321#define ADP_DP_CS_0_AE BIT(30) 322#define ADP_DP_CS_0_VE BIT(31) 323#define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0) --- 97 unchanged lines hidden (view full) --- 421#define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1 422#define TB_LC_POWER 0x740 423 424/* Link controller registers */ 425#define TB_LC_PORT_ATTR 0x8d 426#define TB_LC_PORT_ATTR_BE BIT(12) 427 428#define TB_LC_SX_CTRL 0x96 |
| 429#define TB_LC_SX_CTRL_WOC BIT(1) 430#define TB_LC_SX_CTRL_WOD BIT(2) 431#define TB_LC_SX_CTRL_WOU4 BIT(5) 432#define TB_LC_SX_CTRL_WOP BIT(6) |
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| 421#define TB_LC_SX_CTRL_L1C BIT(16) 422#define TB_LC_SX_CTRL_L1D BIT(17) 423#define TB_LC_SX_CTRL_L2C BIT(20) 424#define TB_LC_SX_CTRL_L2D BIT(21) 425#define TB_LC_SX_CTRL_UPSTREAM BIT(30) 426#define TB_LC_SX_CTRL_SLP BIT(31) 427 428#endif | 433#define TB_LC_SX_CTRL_L1C BIT(16) 434#define TB_LC_SX_CTRL_L1D BIT(17) 435#define TB_LC_SX_CTRL_L2C BIT(20) 436#define TB_LC_SX_CTRL_L2D BIT(21) 437#define TB_LC_SX_CTRL_UPSTREAM BIT(30) 438#define TB_LC_SX_CTRL_SLP BIT(31) 439 440#endif |