lc.c (5d8dfaa71d87f742c53309b95cb6a8b274119027) | lc.c (43f977bc60b1cfd3c1d220a9a0a06493fbf3985d) |
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1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Thunderbolt link controller support 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 --- 179 unchanged lines hidden (view full) --- 188 if (ret) 189 return ret; 190 191 ctrl |= TB_LC_SX_CTRL_SLI; 192 193 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1); 194} 195 | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Thunderbolt link controller support 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 --- 179 unchanged lines hidden (view full) --- 188 if (ret) 189 return ret; 190 191 ctrl |= TB_LC_SX_CTRL_SLI; 192 193 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1); 194} 195 |
196/** 197 * tb_lc_is_clx_supported() - Check whether CLx is supported by the lane adapter 198 * @port: Lane adapter 199 * 200 * TB_LC_LINK_ATTR_CPS bit reflects if the link supports CLx including 201 * active cables (if connected on the link). 202 */ 203bool tb_lc_is_clx_supported(struct tb_port *port) 204{ 205 struct tb_switch *sw = port->sw; 206 int cap, ret; 207 u32 val; 208 209 cap = find_port_lc_cap(port); 210 if (cap < 0) 211 return false; 212 213 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_ATTR, 1); 214 if (ret) 215 return false; 216 217 return !!(val & TB_LC_LINK_ATTR_CPS); 218} 219 |
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196static int tb_lc_set_wake_one(struct tb_switch *sw, unsigned int offset, 197 unsigned int flags) 198{ 199 u32 ctrl; 200 int ret; 201 202 /* 203 * Enable wake on PCIe and USB4 (wake coming from another --- 307 unchanged lines hidden --- | 220static int tb_lc_set_wake_one(struct tb_switch *sw, unsigned int offset, 221 unsigned int flags) 222{ 223 u32 ctrl; 224 int ret; 225 226 /* 227 * Enable wake on PCIe and USB4 (wake coming from another --- 307 unchanged lines hidden --- |