lc.c (284652a4a49917e121277a6cacbefed9f65b94ca) lc.c (b2911a593a705e54adde6d06d4657c1ff2f16583)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Thunderbolt link controller support
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 */
8

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153 *
154 * Unsets the lane XDomain configuration.
155 */
156void tb_lc_unconfigure_xdomain(struct tb_port *port)
157{
158 tb_lc_set_xdomain_configured(port, false);
159}
160
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Thunderbolt link controller support
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 */
8

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153 *
154 * Unsets the lane XDomain configuration.
155 */
156void tb_lc_unconfigure_xdomain(struct tb_port *port)
157{
158 tb_lc_set_xdomain_configured(port, false);
159}
160
161static int tb_lc_set_wake_one(struct tb_switch *sw, unsigned int offset,
162 unsigned int flags)
163{
164 u32 ctrl;
165 int ret;
166
167 /*
168 * Enable wake on PCIe and USB4 (wake coming from another
169 * router).
170 */
171 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
172 offset + TB_LC_SX_CTRL, 1);
173 if (ret)
174 return ret;
175
176 ctrl &= ~(TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD | TB_LC_SX_CTRL_WOP |
177 TB_LC_SX_CTRL_WOU4);
178
179 if (flags & TB_WAKE_ON_CONNECT)
180 ctrl |= TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD;
181 if (flags & TB_WAKE_ON_USB4)
182 ctrl |= TB_LC_SX_CTRL_WOU4;
183 if (flags & TB_WAKE_ON_PCIE)
184 ctrl |= TB_LC_SX_CTRL_WOP;
185
186 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, offset + TB_LC_SX_CTRL, 1);
187}
188
161/**
189/**
190 * tb_lc_set_wake() - Enable/disable wake
191 * @sw: Switch whose wakes to configure
192 * @flags: Wakeup flags (%0 to disable)
193 *
194 * For each LC sets wake bits accordingly.
195 */
196int tb_lc_set_wake(struct tb_switch *sw, unsigned int flags)
197{
198 int start, size, nlc, ret, i;
199 u32 desc;
200
201 if (sw->generation < 2)
202 return 0;
203
204 if (!tb_route(sw))
205 return 0;
206
207 ret = read_lc_desc(sw, &desc);
208 if (ret)
209 return ret;
210
211 /* Figure out number of link controllers */
212 nlc = desc & TB_LC_DESC_NLC_MASK;
213 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
214 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
215
216 /* For each link controller set sleep bit */
217 for (i = 0; i < nlc; i++) {
218 unsigned int offset = sw->cap_lc + start + i * size;
219
220 ret = tb_lc_set_wake_one(sw, offset, flags);
221 if (ret)
222 return ret;
223 }
224
225 return 0;
226}
227
228/**
162 * tb_lc_set_sleep() - Inform LC that the switch is going to sleep
163 * @sw: Switch to set sleep
164 *
165 * Let the switch link controllers know that the switch is going to
166 * sleep.
167 */
168int tb_lc_set_sleep(struct tb_switch *sw)
169{

--- 237 unchanged lines hidden --- 		229 * tb_lc_set_sleep() - Inform LC that the switch is going to sleep
230 * @sw: Switch to set sleep
231 *
232 * Let the switch link controllers know that the switch is going to
233 * sleep.
234 */
235int tb_lc_set_sleep(struct tb_switch *sw)
236{

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