spi-pxa2xx.h (bf61c8840efe60fd8f91446860b63338fb424158) spi-pxa2xx.h (e5262d0568dc9e10de79a726dfd7edb712a2c10b)
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */

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88 void (*cs_control)(u32 command);
89
90 void __iomem *lpss_base;
91};
92
93struct chip_data {
94 u32 cr0;
95 u32 cr1;
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */

--- 79 unchanged lines hidden (view full) ---

88 void (*cs_control)(u32 command);
89
90 void __iomem *lpss_base;
91};
92
93struct chip_data {
94 u32 cr0;
95 u32 cr1;
96 u32 dds_rate;
96 u32 psp;
97 u32 timeout;
98 u8 n_bytes;
99 u32 dma_burst_size;
100 u32 threshold;
101 u32 dma_threshold;
102 u16 lpss_rx_threshold;
103 u16 lpss_tx_threshold;

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121static inline void write_##reg(u32 v, void __iomem *p) \
122{ __raw_writel(v, p + (off)); }
123
124DEFINE_SSP_REG(SSCR0, 0x00)
125DEFINE_SSP_REG(SSCR1, 0x04)
126DEFINE_SSP_REG(SSSR, 0x08)
127DEFINE_SSP_REG(SSITR, 0x0c)
128DEFINE_SSP_REG(SSDR, 0x10)
97 u32 psp;
98 u32 timeout;
99 u8 n_bytes;
100 u32 dma_burst_size;
101 u32 threshold;
102 u32 dma_threshold;
103 u16 lpss_rx_threshold;
104 u16 lpss_tx_threshold;

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122static inline void write_##reg(u32 v, void __iomem *p) \
123{ __raw_writel(v, p + (off)); }
124
125DEFINE_SSP_REG(SSCR0, 0x00)
126DEFINE_SSP_REG(SSCR1, 0x04)
127DEFINE_SSP_REG(SSSR, 0x08)
128DEFINE_SSP_REG(SSITR, 0x0c)
129DEFINE_SSP_REG(SSDR, 0x10)
130DEFINE_SSP_REG(DDS_RATE, 0x28) /* DDS Clock Rate */
129DEFINE_SSP_REG(SSTO, 0x28)
130DEFINE_SSP_REG(SSPSP, 0x2c)
131DEFINE_SSP_REG(SSITF, SSITF)
132DEFINE_SSP_REG(SSIRF, SSIRF)
133
134#define START_STATE ((void *)0)
135#define RUNNING_STATE ((void *)1)
136#define DONE_STATE ((void *)2)
137#define ERROR_STATE ((void *)-1)
138
139#define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
140#define DMA_ALIGNMENT 8
141
142static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
143{
131DEFINE_SSP_REG(SSTO, 0x28)
132DEFINE_SSP_REG(SSPSP, 0x2c)
133DEFINE_SSP_REG(SSITF, SSITF)
134DEFINE_SSP_REG(SSIRF, SSIRF)
135
136#define START_STATE ((void *)0)
137#define RUNNING_STATE ((void *)1)
138#define DONE_STATE ((void *)2)
139#define ERROR_STATE ((void *)-1)
140
141#define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
142#define DMA_ALIGNMENT 8
143
144static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
145{
144 if (drv_data->ssp_type == PXA25x_SSP)
146 switch (drv_data->ssp_type) {
147 case PXA25x_SSP:
148 case CE4100_SSP:
149 case QUARK_X1000_SSP:
145 return 1;
150 return 1;
146 if (drv_data->ssp_type == CE4100_SSP)
147 return 1;
148 return 0;
151 default:
152 return 0;
153 }
149}
150
151static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
152{
153 void __iomem *reg = drv_data->ioaddr;
154
154}
155
156static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
157{
158 void __iomem *reg = drv_data->ioaddr;
159
155 if (drv_data->ssp_type == CE4100_SSP)
160 if (drv_data->ssp_type == CE4100_SSP ||
161 drv_data->ssp_type == QUARK_X1000_SSP)
156 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
157
158 write_SSSR(val, reg);
159}
160
161extern int pxa2xx_spi_flush(struct driver_data *drv_data);
162extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
163

--- 58 unchanged lines hidden --- 		162 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
163
164 write_SSSR(val, reg);
165}
166
167extern int pxa2xx_spi_flush(struct driver_data *drv_data);
168extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
169

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