spi-pxa2xx.c (b3d6cfd09184dcea17f7d8e29c71fafe58bb5f00) spi-pxa2xx.c (e5262d0568dc9e10de79a726dfd7edb712a2c10b)
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

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58 */
59#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
60 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
61 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
62 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
63 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

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58 */
59#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
60 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
61 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
62 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
63 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65
66#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
67 | QUARK_X1000_SSCR1_EFWR \
68 | QUARK_X1000_SSCR1_RFT \
69 | QUARK_X1000_SSCR1_TFT \
70 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
71
66#define LPSS_RX_THRESH_DFLT 64
67#define LPSS_TX_LOTHRESH_DFLT 160
68#define LPSS_TX_HITHRESH_DFLT 224
69
72#define LPSS_RX_THRESH_DFLT 64
73#define LPSS_TX_LOTHRESH_DFLT 160
74#define LPSS_TX_HITHRESH_DFLT 224
75
76struct quark_spi_rate {
77 u32 bitrate;
78 u32 dds_clk_rate;
79 u32 clk_div;
80};
81
82/*
83 * 'rate', 'dds', 'clk_div' lookup table, which is defined in
84 * the Quark SPI datasheet.
85 */
86static const struct quark_spi_rate quark_spi_rate_table[] = {
87/* bitrate, dds_clk_rate, clk_div */
88 {50000000, 0x800000, 0},
89 {40000000, 0x666666, 0},
90 {25000000, 0x400000, 0},
91 {20000000, 0x666666, 1},
92 {16667000, 0x800000, 2},
93 {13333000, 0x666666, 2},
94 {12500000, 0x200000, 0},
95 {10000000, 0x800000, 4},
96 {8000000, 0x666666, 4},
97 {6250000, 0x400000, 3},
98 {5000000, 0x400000, 4},
99 {4000000, 0x666666, 9},
100 {3125000, 0x80000, 0},
101 {2500000, 0x400000, 9},
102 {2000000, 0x666666, 19},
103 {1563000, 0x40000, 0},
104 {1250000, 0x200000, 9},
105 {1000000, 0x400000, 24},
106 {800000, 0x666666, 49},
107 {781250, 0x20000, 0},
108 {625000, 0x200000, 19},
109 {500000, 0x400000, 49},
110 {400000, 0x666666, 99},
111 {390625, 0x10000, 0},
112 {250000, 0x400000, 99},
113 {200000, 0x666666, 199},
114 {195313, 0x8000, 0},
115 {125000, 0x100000, 49},
116 {100000, 0x200000, 124},
117 {50000, 0x100000, 124},
118 {25000, 0x80000, 124},
119 {10016, 0x20000, 77},
120 {5040, 0x20000, 154},
121 {1002, 0x8000, 194},
122};
123
70/* Offset from drv_data->lpss_base */
71#define GENERAL_REG 0x08
72#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
73#define SSP_REG 0x0c
74#define SPI_CS_CONTROL 0x18
75#define SPI_CS_CONTROL_SW_MODE BIT(0)
76#define SPI_CS_CONTROL_CS_HIGH BIT(1)
77
78static bool is_lpss_ssp(const struct driver_data *drv_data)
79{
80 return drv_data->ssp_type == LPSS_SSP;
81}
82
124/* Offset from drv_data->lpss_base */
125#define GENERAL_REG 0x08
126#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
127#define SSP_REG 0x0c
128#define SPI_CS_CONTROL 0x18
129#define SPI_CS_CONTROL_SW_MODE BIT(0)
130#define SPI_CS_CONTROL_CS_HIGH BIT(1)
131
132static bool is_lpss_ssp(const struct driver_data *drv_data)
133{
134 return drv_data->ssp_type == LPSS_SSP;
135}
136
137static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
138{
139 return drv_data->ssp_type == QUARK_X1000_SSP;
140}
141
142static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
143{
144 switch (drv_data->ssp_type) {
145 case QUARK_X1000_SSP:
146 return QUARK_X1000_SSCR1_CHANGE_MASK;
147 default:
148 return SSCR1_CHANGE_MASK;
149 }
150}
151
152static u32
153pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
154{
155 switch (drv_data->ssp_type) {
156 case QUARK_X1000_SSP:
157 return RX_THRESH_QUARK_X1000_DFLT;
158 default:
159 return RX_THRESH_DFLT;
160 }
161}
162
163static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
164{
165 void __iomem *reg = drv_data->ioaddr;
166 u32 mask;
167
168 switch (drv_data->ssp_type) {
169 case QUARK_X1000_SSP:
170 mask = QUARK_X1000_SSSR_TFL_MASK;
171 break;
172 default:
173 mask = SSSR_TFL_MASK;
174 break;
175 }
176
177 return (read_SSSR(reg) & mask) == mask;
178}
179
180static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
181 u32 *sccr1_reg)
182{
183 u32 mask;
184
185 switch (drv_data->ssp_type) {
186 case QUARK_X1000_SSP:
187 mask = QUARK_X1000_SSCR1_RFT;
188 break;
189 default:
190 mask = SSCR1_RFT;
191 break;
192 }
193 *sccr1_reg &= ~mask;
194}
195
196static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
197 u32 *sccr1_reg, u32 threshold)
198{
199 switch (drv_data->ssp_type) {
200 case QUARK_X1000_SSP:
201 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
202 break;
203 default:
204 *sccr1_reg |= SSCR1_RxTresh(threshold);
205 break;
206 }
207}
208
209static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
210 u32 clk_div, u8 bits)
211{
212 switch (drv_data->ssp_type) {
213 case QUARK_X1000_SSP:
214 return clk_div
215 | QUARK_X1000_SSCR0_Motorola
216 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
217 | SSCR0_SSE;
218 default:
219 return clk_div
220 | SSCR0_Motorola
221 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
222 | SSCR0_SSE
223 | (bits > 16 ? SSCR0_EDSS : 0);
224 }
225}
226
83/*
84 * Read and write LPSS SSP private registers. Caller must first check that
85 * is_lpss_ssp() returns true before these can be called.
86 */
87static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
88{
89 WARN_ON(!drv_data->lpss_base);
90 return readl(drv_data->lpss_base + offset);

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229 return limit;
230}
231
232static int null_writer(struct driver_data *drv_data)
233{
234 void __iomem *reg = drv_data->ioaddr;
235 u8 n_bytes = drv_data->n_bytes;
236
227/*
228 * Read and write LPSS SSP private registers. Caller must first check that
229 * is_lpss_ssp() returns true before these can be called.
230 */
231static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
232{
233 WARN_ON(!drv_data->lpss_base);
234 return readl(drv_data->lpss_base + offset);

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373 return limit;
374}
375
376static int null_writer(struct driver_data *drv_data)
377{
378 void __iomem *reg = drv_data->ioaddr;
379 u8 n_bytes = drv_data->n_bytes;
380
237 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
381 if (pxa2xx_spi_txfifo_full(drv_data)
238 || (drv_data->tx == drv_data->tx_end))
239 return 0;
240
241 write_SSDR(0, reg);
242 drv_data->tx += n_bytes;
243
244 return 1;
245}

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257
258 return drv_data->rx == drv_data->rx_end;
259}
260
261static int u8_writer(struct driver_data *drv_data)
262{
263 void __iomem *reg = drv_data->ioaddr;
264
382 || (drv_data->tx == drv_data->tx_end))
383 return 0;
384
385 write_SSDR(0, reg);
386 drv_data->tx += n_bytes;
387
388 return 1;
389}

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401
402 return drv_data->rx == drv_data->rx_end;
403}
404
405static int u8_writer(struct driver_data *drv_data)
406{
407 void __iomem *reg = drv_data->ioaddr;
408
265 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
409 if (pxa2xx_spi_txfifo_full(drv_data)
266 || (drv_data->tx == drv_data->tx_end))
267 return 0;
268
269 write_SSDR(*(u8 *)(drv_data->tx), reg);
270 ++drv_data->tx;
271
272 return 1;
273}

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284
285 return drv_data->rx == drv_data->rx_end;
286}
287
288static int u16_writer(struct driver_data *drv_data)
289{
290 void __iomem *reg = drv_data->ioaddr;
291
410 || (drv_data->tx == drv_data->tx_end))
411 return 0;
412
413 write_SSDR(*(u8 *)(drv_data->tx), reg);
414 ++drv_data->tx;
415
416 return 1;
417}

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428
429 return drv_data->rx == drv_data->rx_end;
430}
431
432static int u16_writer(struct driver_data *drv_data)
433{
434 void __iomem *reg = drv_data->ioaddr;
435
292 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
436 if (pxa2xx_spi_txfifo_full(drv_data)
293 || (drv_data->tx == drv_data->tx_end))
294 return 0;
295
296 write_SSDR(*(u16 *)(drv_data->tx), reg);
297 drv_data->tx += 2;
298
299 return 1;
300}

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311
312 return drv_data->rx == drv_data->rx_end;
313}
314
315static int u32_writer(struct driver_data *drv_data)
316{
317 void __iomem *reg = drv_data->ioaddr;
318
437 || (drv_data->tx == drv_data->tx_end))
438 return 0;
439
440 write_SSDR(*(u16 *)(drv_data->tx), reg);
441 drv_data->tx += 2;
442
443 return 1;
444}

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455
456 return drv_data->rx == drv_data->rx_end;
457}
458
459static int u32_writer(struct driver_data *drv_data)
460{
461 void __iomem *reg = drv_data->ioaddr;
462
319 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
463 if (pxa2xx_spi_txfifo_full(drv_data)
320 || (drv_data->tx == drv_data->tx_end))
321 return 0;
322
323 write_SSDR(*(u32 *)(drv_data->tx), reg);
324 drv_data->tx += 4;
325
326 return 1;
327}

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503 sccr1_reg = read_SSCR1(reg);
504 sccr1_reg &= ~SSCR1_TIE;
505
506 /*
507 * PXA25x_SSP has no timeout, set up rx threshould for the
508 * remaining RX bytes.
509 */
510 if (pxa25x_ssp_comp(drv_data)) {
464 || (drv_data->tx == drv_data->tx_end))
465 return 0;
466
467 write_SSDR(*(u32 *)(drv_data->tx), reg);
468 drv_data->tx += 4;
469
470 return 1;
471}

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647 sccr1_reg = read_SSCR1(reg);
648 sccr1_reg &= ~SSCR1_TIE;
649
650 /*
651 * PXA25x_SSP has no timeout, set up rx threshould for the
652 * remaining RX bytes.
653 */
654 if (pxa25x_ssp_comp(drv_data)) {
655 u32 rx_thre;
511
656
512 sccr1_reg &= ~SSCR1_RFT;
657 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
513
514 bytes_left = drv_data->rx_end - drv_data->rx;
515 switch (drv_data->n_bytes) {
516 case 4:
517 bytes_left >>= 1;
518 case 2:
519 bytes_left >>= 1;
520 }
521
658
659 bytes_left = drv_data->rx_end - drv_data->rx;
660 switch (drv_data->n_bytes) {
661 case 4:
662 bytes_left >>= 1;
663 case 2:
664 bytes_left >>= 1;
665 }
666
522 if (bytes_left > RX_THRESH_DFLT)
523 bytes_left = RX_THRESH_DFLT;
667 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
668 if (rx_thre > bytes_left)
669 rx_thre = bytes_left;
524
670
525 sccr1_reg |= SSCR1_RxTresh(bytes_left);
671 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
526 }
527 write_SSCR1(sccr1_reg, reg);
528 }
529
530 /* We did something */
531 return IRQ_HANDLED;
532}
533

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580
581 /* Never fail */
582 return IRQ_HANDLED;
583 }
584
585 return drv_data->transfer_handler(drv_data);
586}
587
672 }
673 write_SSCR1(sccr1_reg, reg);
674 }
675
676 /* We did something */
677 return IRQ_HANDLED;
678}
679

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726
727 /* Never fail */
728 return IRQ_HANDLED;
729 }
730
731 return drv_data->transfer_handler(drv_data);
732}
733
734/*
735 * The Quark SPI data sheet gives a table, and for the given 'rate',
736 * the 'dds' and 'clk_div' can be found in the table.
737 */
738static u32 quark_x1000_set_clk_regvals(u32 rate, u32 *dds, u32 *clk_div)
739{
740 unsigned int i;
741
742 for (i = 0; i < ARRAY_SIZE(quark_spi_rate_table); i++) {
743 if (rate >= quark_spi_rate_table[i].bitrate) {
744 *dds = quark_spi_rate_table[i].dds_clk_rate;
745 *clk_div = quark_spi_rate_table[i].clk_div;
746 return quark_spi_rate_table[i].bitrate;
747 }
748 }
749
750 *dds = quark_spi_rate_table[i-1].dds_clk_rate;
751 *clk_div = quark_spi_rate_table[i-1].clk_div;
752
753 return quark_spi_rate_table[i-1].bitrate;
754}
755
588static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
589{
590 unsigned long ssp_clk = drv_data->max_clk_rate;
591 const struct ssp_device *ssp = drv_data->ssp;
592
593 rate = min_t(int, ssp_clk, rate);
594
595 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
596 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
597 else
598 return ((ssp_clk / rate - 1) & 0xfff) << 8;
599}
600
756static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
757{
758 unsigned long ssp_clk = drv_data->max_clk_rate;
759 const struct ssp_device *ssp = drv_data->ssp;
760
761 rate = min_t(int, ssp_clk, rate);
762
763 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
764 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
765 else
766 return ((ssp_clk / rate - 1) & 0xfff) << 8;
767}
768
769static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
770 struct chip_data *chip, int rate)
771{
772 u32 clk_div;
773
774 switch (drv_data->ssp_type) {
775 case QUARK_X1000_SSP:
776 quark_x1000_set_clk_regvals(rate, &chip->dds_rate, &clk_div);
777 return clk_div << 8;
778 default:
779 return ssp_get_clk_div(drv_data, rate);
780 }
781}
782
601static void pump_transfers(unsigned long data)
602{
603 struct driver_data *drv_data = (struct driver_data *)data;
604 struct spi_message *message = NULL;
605 struct spi_transfer *transfer = NULL;
606 struct spi_transfer *previous = NULL;
607 struct chip_data *chip = NULL;
608 void __iomem *reg = drv_data->ioaddr;
609 u32 clk_div = 0;
610 u8 bits = 0;
611 u32 speed = 0;
612 u32 cr0;
613 u32 cr1;
614 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
615 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
783static void pump_transfers(unsigned long data)
784{
785 struct driver_data *drv_data = (struct driver_data *)data;
786 struct spi_message *message = NULL;
787 struct spi_transfer *transfer = NULL;
788 struct spi_transfer *previous = NULL;
789 struct chip_data *chip = NULL;
790 void __iomem *reg = drv_data->ioaddr;
791 u32 clk_div = 0;
792 u8 bits = 0;
793 u32 speed = 0;
794 u32 cr0;
795 u32 cr1;
796 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
797 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
798 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
616
617 /* Get current state information */
618 message = drv_data->cur_msg;
619 transfer = drv_data->cur_transfer;
620 chip = drv_data->cur_chip;
621
622 /* Handle for abort */
623 if (message->state == ERROR_STATE) {

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694 speed = chip->speed_hz;
695
696 if (transfer->speed_hz)
697 speed = transfer->speed_hz;
698
699 if (transfer->bits_per_word)
700 bits = transfer->bits_per_word;
701
799
800 /* Get current state information */
801 message = drv_data->cur_msg;
802 transfer = drv_data->cur_transfer;
803 chip = drv_data->cur_chip;
804
805 /* Handle for abort */
806 if (message->state == ERROR_STATE) {

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877 speed = chip->speed_hz;
878
879 if (transfer->speed_hz)
880 speed = transfer->speed_hz;
881
882 if (transfer->bits_per_word)
883 bits = transfer->bits_per_word;
884
702 clk_div = ssp_get_clk_div(drv_data, speed);
885 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed);
703
704 if (bits <= 8) {
705 drv_data->n_bytes = 1;
706 drv_data->read = drv_data->read != null_reader ?
707 u8_reader : null_reader;
708 drv_data->write = drv_data->write != null_writer ?
709 u8_writer : null_writer;
710 } else if (bits <= 16) {

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726 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
727 message->spi,
728 bits, &dma_burst,
729 &dma_thresh))
730 dev_warn_ratelimited(&message->spi->dev,
731 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
732 }
733
886
887 if (bits <= 8) {
888 drv_data->n_bytes = 1;
889 drv_data->read = drv_data->read != null_reader ?
890 u8_reader : null_reader;
891 drv_data->write = drv_data->write != null_writer ?
892 u8_writer : null_writer;
893 } else if (bits <= 16) {

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909 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
910 message->spi,
911 bits, &dma_burst,
912 &dma_thresh))
913 dev_warn_ratelimited(&message->spi->dev,
914 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
915 }
916
734 cr0 = clk_div
735 | SSCR0_Motorola
736 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
737 | SSCR0_SSE
738 | (bits > 16 ? SSCR0_EDSS : 0);
917 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
739 }
740
741 message->state = RUNNING_STATE;
742
743 drv_data->dma_mapped = 0;
744 if (pxa2xx_spi_dma_is_possible(drv_data->len))
745 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
746 if (drv_data->dma_mapped) {

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766
767 if (is_lpss_ssp(drv_data)) {
768 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
769 write_SSIRF(chip->lpss_rx_threshold, reg);
770 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
771 write_SSITF(chip->lpss_tx_threshold, reg);
772 }
773
918 }
919
920 message->state = RUNNING_STATE;
921
922 drv_data->dma_mapped = 0;
923 if (pxa2xx_spi_dma_is_possible(drv_data->len))
924 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
925 if (drv_data->dma_mapped) {

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945
946 if (is_lpss_ssp(drv_data)) {
947 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
948 write_SSIRF(chip->lpss_rx_threshold, reg);
949 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
950 write_SSITF(chip->lpss_tx_threshold, reg);
951 }
952
953 if (is_quark_x1000_ssp(drv_data) &&
954 (read_DDS_RATE(reg) != chip->dds_rate))
955 write_DDS_RATE(chip->dds_rate, reg);
956
774 /* see if we need to reload the config registers */
957 /* see if we need to reload the config registers */
775 if ((read_SSCR0(reg) != cr0)
776 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
777 (cr1 & SSCR1_CHANGE_MASK)) {
958 if ((read_SSCR0(reg) != cr0) ||
959 (read_SSCR1(reg) & change_mask) != (cr1 & change_mask)) {
778
779 /* stop the SSP, and update the other bits */
780 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
781 if (!pxa25x_ssp_comp(drv_data))
782 write_SSTO(chip->timeout, reg);
783 /* first set CR1 without interrupt and service enables */
960
961 /* stop the SSP, and update the other bits */
962 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
963 if (!pxa25x_ssp_comp(drv_data))
964 write_SSTO(chip->timeout, reg);
965 /* first set CR1 without interrupt and service enables */
784 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
966 write_SSCR1(cr1 & change_mask, reg);
785 /* restart the SSP */
786 write_SSCR0(cr0, reg);
787
788 } else {
789 if (!pxa25x_ssp_comp(drv_data))
790 write_SSTO(chip->timeout, reg);
791 }
792

--- 77 unchanged lines hidden (view full) ---

870static int setup(struct spi_device *spi)
871{
872 struct pxa2xx_spi_chip *chip_info = NULL;
873 struct chip_data *chip;
874 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
875 unsigned int clk_div;
876 uint tx_thres, tx_hi_thres, rx_thres;
877
967 /* restart the SSP */
968 write_SSCR0(cr0, reg);
969
970 } else {
971 if (!pxa25x_ssp_comp(drv_data))
972 write_SSTO(chip->timeout, reg);
973 }
974

--- 77 unchanged lines hidden (view full) ---

1052static int setup(struct spi_device *spi)
1053{
1054 struct pxa2xx_spi_chip *chip_info = NULL;
1055 struct chip_data *chip;
1056 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1057 unsigned int clk_div;
1058 uint tx_thres, tx_hi_thres, rx_thres;
1059
878 if (is_lpss_ssp(drv_data)) {
1060 switch (drv_data->ssp_type) {
1061 case QUARK_X1000_SSP:
1062 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1063 tx_hi_thres = 0;
1064 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1065 break;
1066 case LPSS_SSP:
879 tx_thres = LPSS_TX_LOTHRESH_DFLT;
880 tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
881 rx_thres = LPSS_RX_THRESH_DFLT;
1067 tx_thres = LPSS_TX_LOTHRESH_DFLT;
1068 tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
1069 rx_thres = LPSS_RX_THRESH_DFLT;
882 } else {
1070 break;
1071 default:
883 tx_thres = TX_THRESH_DFLT;
884 tx_hi_thres = 0;
885 rx_thres = RX_THRESH_DFLT;
1072 tx_thres = TX_THRESH_DFLT;
1073 tx_hi_thres = 0;
1074 rx_thres = RX_THRESH_DFLT;
1075 break;
886 }
887
888 /* Only alloc on first setup */
889 chip = spi_get_ctldata(spi);
890 if (!chip) {
891 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
892 if (!chip)
893 return -ENOMEM;

--- 36 unchanged lines hidden (view full) ---

930 /*
931 * Slave devices enumerated from ACPI namespace don't
932 * usually have chip_info but we still might want to use
933 * DMA with them.
934 */
935 chip->enable_dma = drv_data->master_info->enable_dma;
936 }
937
1076 }
1077
1078 /* Only alloc on first setup */
1079 chip = spi_get_ctldata(spi);
1080 if (!chip) {
1081 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1082 if (!chip)
1083 return -ENOMEM;

--- 36 unchanged lines hidden (view full) ---

1120 /*
1121 * Slave devices enumerated from ACPI namespace don't
1122 * usually have chip_info but we still might want to use
1123 * DMA with them.
1124 */
1125 chip->enable_dma = drv_data->master_info->enable_dma;
1126 }
1127
938 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
939 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
940
941 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
942 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
943 | SSITF_TxHiThresh(tx_hi_thres);
944
945 /* set dma burst and threshold outside of chip_info path so that if
946 * chip_info goes away after setting chip->enable_dma, the
947 * burst and threshold can still respond to changes in bits_per_word */
948 if (chip->enable_dma) {
949 /* set up legal burst and threshold for dma */
950 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
951 spi->bits_per_word,
952 &chip->dma_burst_size,
953 &chip->dma_threshold)) {
954 dev_warn(&spi->dev,
955 "in setup: DMA burst size reduced to match bits_per_word\n");
956 }
957 }
958
1128 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1129 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1130 | SSITF_TxHiThresh(tx_hi_thres);
1131
1132 /* set dma burst and threshold outside of chip_info path so that if
1133 * chip_info goes away after setting chip->enable_dma, the
1134 * burst and threshold can still respond to changes in bits_per_word */
1135 if (chip->enable_dma) {
1136 /* set up legal burst and threshold for dma */
1137 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1138 spi->bits_per_word,
1139 &chip->dma_burst_size,
1140 &chip->dma_threshold)) {
1141 dev_warn(&spi->dev,
1142 "in setup: DMA burst size reduced to match bits_per_word\n");
1143 }
1144 }
1145
959 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
1146 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
960 chip->speed_hz = spi->max_speed_hz;
961
1147 chip->speed_hz = spi->max_speed_hz;
1148
962 chip->cr0 = clk_div
963 | SSCR0_Motorola
964 | SSCR0_DataSize(spi->bits_per_word > 16 ?
965 spi->bits_per_word - 16 : spi->bits_per_word)
966 | SSCR0_SSE
967 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1149 chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div,
1150 spi->bits_per_word);
1151 switch (drv_data->ssp_type) {
1152 case QUARK_X1000_SSP:
1153 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1154 & QUARK_X1000_SSCR1_RFT)
1155 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1156 & QUARK_X1000_SSCR1_TFT);
1157 break;
1158 default:
1159 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1160 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1161 break;
1162 }
1163
968 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
969 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
970 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
971
972 if (spi->mode & SPI_LOOP)
973 chip->cr1 |= SSCR1_LBM;
974
975 /* NOTE: PXA25x_SSP _could_ use external clocking ... */

--- 12 unchanged lines hidden (view full) ---

988 chip->n_bytes = 1;
989 chip->read = u8_reader;
990 chip->write = u8_writer;
991 } else if (spi->bits_per_word <= 16) {
992 chip->n_bytes = 2;
993 chip->read = u16_reader;
994 chip->write = u16_writer;
995 } else if (spi->bits_per_word <= 32) {
1164 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1165 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1166 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1167
1168 if (spi->mode & SPI_LOOP)
1169 chip->cr1 |= SSCR1_LBM;
1170
1171 /* NOTE: PXA25x_SSP _could_ use external clocking ... */

--- 12 unchanged lines hidden (view full) ---

1184 chip->n_bytes = 1;
1185 chip->read = u8_reader;
1186 chip->write = u8_writer;
1187 } else if (spi->bits_per_word <= 16) {
1188 chip->n_bytes = 2;
1189 chip->read = u16_reader;
1190 chip->write = u16_writer;
1191 } else if (spi->bits_per_word <= 32) {
996 chip->cr0 |= SSCR0_EDSS;
1192 if (!is_quark_x1000_ssp(drv_data))
1193 chip->cr0 |= SSCR0_EDSS;
997 chip->n_bytes = 4;
998 chip->read = u32_reader;
999 chip->write = u32_writer;
1000 }
1001 chip->bits_per_word = spi->bits_per_word;
1002
1003 spi_set_ctldata(spi, chip);
1004

--- 134 unchanged lines hidden (view full) ---

1139 master->auto_runtime_pm = true;
1140
1141 drv_data->ssp_type = ssp->type;
1142 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1143
1144 drv_data->ioaddr = ssp->mmio_base;
1145 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1146 if (pxa25x_ssp_comp(drv_data)) {
1194 chip->n_bytes = 4;
1195 chip->read = u32_reader;
1196 chip->write = u32_writer;
1197 }
1198 chip->bits_per_word = spi->bits_per_word;
1199
1200 spi_set_ctldata(spi, chip);
1201

--- 134 unchanged lines hidden (view full) ---

1336 master->auto_runtime_pm = true;
1337
1338 drv_data->ssp_type = ssp->type;
1339 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1340
1341 drv_data->ioaddr = ssp->mmio_base;
1342 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1343 if (pxa25x_ssp_comp(drv_data)) {
1147 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1344 switch (drv_data->ssp_type) {
1345 case QUARK_X1000_SSP:
1346 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1347 break;
1348 default:
1349 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1350 break;
1351 }
1352
1148 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1149 drv_data->dma_cr1 = 0;
1150 drv_data->clear_sr = SSSR_ROR;
1151 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1152 } else {
1153 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1154 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1155 drv_data->dma_cr1 = DEFAULT_DMA_CR1;

--- 21 unchanged lines hidden (view full) ---

1177
1178 /* Enable SOC clock */
1179 clk_prepare_enable(ssp->clk);
1180
1181 drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1182
1183 /* Load default SSP configuration */
1184 write_SSCR0(0, drv_data->ioaddr);
1353 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1354 drv_data->dma_cr1 = 0;
1355 drv_data->clear_sr = SSSR_ROR;
1356 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1357 } else {
1358 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1359 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1360 drv_data->dma_cr1 = DEFAULT_DMA_CR1;

--- 21 unchanged lines hidden (view full) ---

1382
1383 /* Enable SOC clock */
1384 clk_prepare_enable(ssp->clk);
1385
1386 drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1387
1388 /* Load default SSP configuration */
1389 write_SSCR0(0, drv_data->ioaddr);
1185 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1186 SSCR1_TxTresh(TX_THRESH_DFLT),
1187 drv_data->ioaddr);
1188 write_SSCR0(SSCR0_SCR(2)
1189 | SSCR0_Motorola
1190 | SSCR0_DataSize(8),
1191 drv_data->ioaddr);
1390 switch (drv_data->ssp_type) {
1391 case QUARK_X1000_SSP:
1392 write_SSCR1(QUARK_X1000_SSCR1_RxTresh(
1393 RX_THRESH_QUARK_X1000_DFLT) |
1394 QUARK_X1000_SSCR1_TxTresh(
1395 TX_THRESH_QUARK_X1000_DFLT),
1396 drv_data->ioaddr);
1397
1398 /* using the Motorola SPI protocol and use 8 bit frame */
1399 write_SSCR0(QUARK_X1000_SSCR0_Motorola
1400 | QUARK_X1000_SSCR0_DataSize(8),
1401 drv_data->ioaddr);
1402 break;
1403 default:
1404 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1405 SSCR1_TxTresh(TX_THRESH_DFLT),
1406 drv_data->ioaddr);
1407 write_SSCR0(SSCR0_SCR(2)
1408 | SSCR0_Motorola
1409 | SSCR0_DataSize(8),
1410 drv_data->ioaddr);
1411 break;
1412 }
1413
1192 if (!pxa25x_ssp_comp(drv_data))
1193 write_SSTO(0, drv_data->ioaddr);
1414 if (!pxa25x_ssp_comp(drv_data))
1415 write_SSTO(0, drv_data->ioaddr);
1194 write_SSPSP(0, drv_data->ioaddr);
1195
1416
1417 if (!is_quark_x1000_ssp(drv_data))
1418 write_SSPSP(0, drv_data->ioaddr);
1419
1196 lpss_ssp_setup(drv_data);
1197
1198 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1199 (unsigned long)drv_data);
1200
1201 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1202 pm_runtime_use_autosuspend(&pdev->dev);
1203 pm_runtime_set_active(&pdev->dev);

--- 153 unchanged lines hidden --- 		1420 lpss_ssp_setup(drv_data);
1421
1422 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1423 (unsigned long)drv_data);
1424
1425 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1426 pm_runtime_use_autosuspend(&pdev->dev);
1427 pm_runtime_set_active(&pdev->dev);

--- 153 unchanged lines hidden ---