spi-pxa2xx.c (66e6a5a1fcd2f3e05f4d499b539a1f77ceb52d1d) spi-pxa2xx.c (4fdb2424cc4499237197a8c9d35b34d68c750475)
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

--- 66 unchanged lines hidden (view full) ---

75#define SPI_CS_CONTROL_SW_MODE BIT(0)
76#define SPI_CS_CONTROL_CS_HIGH BIT(1)
77
78static bool is_lpss_ssp(const struct driver_data *drv_data)
79{
80 return drv_data->ssp_type == LPSS_SSP;
81}
82
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

--- 66 unchanged lines hidden (view full) ---

75#define SPI_CS_CONTROL_SW_MODE BIT(0)
76#define SPI_CS_CONTROL_CS_HIGH BIT(1)
77
78static bool is_lpss_ssp(const struct driver_data *drv_data)
79{
80 return drv_data->ssp_type == LPSS_SSP;
81}
82
83static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
84{
85 switch (drv_data->ssp_type) {
86 default:
87 return SSCR1_CHANGE_MASK;
88 }
89}
90
91static u32
92pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
93{
94 switch (drv_data->ssp_type) {
95 default:
96 return RX_THRESH_DFLT;
97 }
98}
99
100static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
101{
102 void __iomem *reg = drv_data->ioaddr;
103 u32 mask;
104
105 switch (drv_data->ssp_type) {
106 default:
107 mask = SSSR_TFL_MASK;
108 break;
109 }
110
111 return (read_SSSR(reg) & mask) == mask;
112}
113
114static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
115 u32 *sccr1_reg)
116{
117 u32 mask;
118
119 switch (drv_data->ssp_type) {
120 default:
121 mask = SSCR1_RFT;
122 break;
123 }
124 *sccr1_reg &= ~mask;
125}
126
127static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
128 u32 *sccr1_reg, u32 threshold)
129{
130 switch (drv_data->ssp_type) {
131 default:
132 *sccr1_reg |= SSCR1_RxTresh(threshold);
133 break;
134 }
135}
136
137static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
138 u32 clk_div, u8 bits)
139{
140 switch (drv_data->ssp_type) {
141 default:
142 return clk_div
143 | SSCR0_Motorola
144 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
145 | SSCR0_SSE
146 | (bits > 16 ? SSCR0_EDSS : 0);
147 }
148}
149
83/*
84 * Read and write LPSS SSP private registers. Caller must first check that
85 * is_lpss_ssp() returns true before these can be called.
86 */
87static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
88{
89 WARN_ON(!drv_data->lpss_base);
90 return readl(drv_data->lpss_base + offset);

--- 138 unchanged lines hidden (view full) ---

229 return limit;
230}
231
232static int null_writer(struct driver_data *drv_data)
233{
234 void __iomem *reg = drv_data->ioaddr;
235 u8 n_bytes = drv_data->n_bytes;
236
150/*
151 * Read and write LPSS SSP private registers. Caller must first check that
152 * is_lpss_ssp() returns true before these can be called.
153 */
154static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
155{
156 WARN_ON(!drv_data->lpss_base);
157 return readl(drv_data->lpss_base + offset);

--- 138 unchanged lines hidden (view full) ---

296 return limit;
297}
298
299static int null_writer(struct driver_data *drv_data)
300{
301 void __iomem *reg = drv_data->ioaddr;
302 u8 n_bytes = drv_data->n_bytes;
303
237 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
304 if (pxa2xx_spi_txfifo_full(drv_data)
238 || (drv_data->tx == drv_data->tx_end))
239 return 0;
240
241 write_SSDR(0, reg);
242 drv_data->tx += n_bytes;
243
244 return 1;
245}

--- 11 unchanged lines hidden (view full) ---

257
258 return drv_data->rx == drv_data->rx_end;
259}
260
261static int u8_writer(struct driver_data *drv_data)
262{
263 void __iomem *reg = drv_data->ioaddr;
264
305 || (drv_data->tx == drv_data->tx_end))
306 return 0;
307
308 write_SSDR(0, reg);
309 drv_data->tx += n_bytes;
310
311 return 1;
312}

--- 11 unchanged lines hidden (view full) ---

324
325 return drv_data->rx == drv_data->rx_end;
326}
327
328static int u8_writer(struct driver_data *drv_data)
329{
330 void __iomem *reg = drv_data->ioaddr;
331
265 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
332 if (pxa2xx_spi_txfifo_full(drv_data)
266 || (drv_data->tx == drv_data->tx_end))
267 return 0;
268
269 write_SSDR(*(u8 *)(drv_data->tx), reg);
270 ++drv_data->tx;
271
272 return 1;
273}

--- 10 unchanged lines hidden (view full) ---

284
285 return drv_data->rx == drv_data->rx_end;
286}
287
288static int u16_writer(struct driver_data *drv_data)
289{
290 void __iomem *reg = drv_data->ioaddr;
291
333 || (drv_data->tx == drv_data->tx_end))
334 return 0;
335
336 write_SSDR(*(u8 *)(drv_data->tx), reg);
337 ++drv_data->tx;
338
339 return 1;
340}

--- 10 unchanged lines hidden (view full) ---

351
352 return drv_data->rx == drv_data->rx_end;
353}
354
355static int u16_writer(struct driver_data *drv_data)
356{
357 void __iomem *reg = drv_data->ioaddr;
358
292 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
359 if (pxa2xx_spi_txfifo_full(drv_data)
293 || (drv_data->tx == drv_data->tx_end))
294 return 0;
295
296 write_SSDR(*(u16 *)(drv_data->tx), reg);
297 drv_data->tx += 2;
298
299 return 1;
300}

--- 10 unchanged lines hidden (view full) ---

311
312 return drv_data->rx == drv_data->rx_end;
313}
314
315static int u32_writer(struct driver_data *drv_data)
316{
317 void __iomem *reg = drv_data->ioaddr;
318
360 || (drv_data->tx == drv_data->tx_end))
361 return 0;
362
363 write_SSDR(*(u16 *)(drv_data->tx), reg);
364 drv_data->tx += 2;
365
366 return 1;
367}

--- 10 unchanged lines hidden (view full) ---

378
379 return drv_data->rx == drv_data->rx_end;
380}
381
382static int u32_writer(struct driver_data *drv_data)
383{
384 void __iomem *reg = drv_data->ioaddr;
385
319 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
386 if (pxa2xx_spi_txfifo_full(drv_data)
320 || (drv_data->tx == drv_data->tx_end))
321 return 0;
322
323 write_SSDR(*(u32 *)(drv_data->tx), reg);
324 drv_data->tx += 4;
325
326 return 1;
327}

--- 175 unchanged lines hidden (view full) ---

503 sccr1_reg = read_SSCR1(reg);
504 sccr1_reg &= ~SSCR1_TIE;
505
506 /*
507 * PXA25x_SSP has no timeout, set up rx threshould for the
508 * remaining RX bytes.
509 */
510 if (pxa25x_ssp_comp(drv_data)) {
387 || (drv_data->tx == drv_data->tx_end))
388 return 0;
389
390 write_SSDR(*(u32 *)(drv_data->tx), reg);
391 drv_data->tx += 4;
392
393 return 1;
394}

--- 175 unchanged lines hidden (view full) ---

570 sccr1_reg = read_SSCR1(reg);
571 sccr1_reg &= ~SSCR1_TIE;
572
573 /*
574 * PXA25x_SSP has no timeout, set up rx threshould for the
575 * remaining RX bytes.
576 */
577 if (pxa25x_ssp_comp(drv_data)) {
578 u32 rx_thre;
511
579
512 sccr1_reg &= ~SSCR1_RFT;
580 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
513
514 bytes_left = drv_data->rx_end - drv_data->rx;
515 switch (drv_data->n_bytes) {
516 case 4:
517 bytes_left >>= 1;
518 case 2:
519 bytes_left >>= 1;
520 }
521
581
582 bytes_left = drv_data->rx_end - drv_data->rx;
583 switch (drv_data->n_bytes) {
584 case 4:
585 bytes_left >>= 1;
586 case 2:
587 bytes_left >>= 1;
588 }
589
522 if (bytes_left > RX_THRESH_DFLT)
523 bytes_left = RX_THRESH_DFLT;
590 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
591 if (rx_thre > bytes_left)
592 rx_thre = bytes_left;
524
593
525 sccr1_reg |= SSCR1_RxTresh(bytes_left);
594 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
526 }
527 write_SSCR1(sccr1_reg, reg);
528 }
529
530 /* We did something */
531 return IRQ_HANDLED;
532}
533

--- 74 unchanged lines hidden (view full) ---

608 void __iomem *reg = drv_data->ioaddr;
609 u32 clk_div = 0;
610 u8 bits = 0;
611 u32 speed = 0;
612 u32 cr0;
613 u32 cr1;
614 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
615 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
595 }
596 write_SSCR1(sccr1_reg, reg);
597 }
598
599 /* We did something */
600 return IRQ_HANDLED;
601}
602

--- 74 unchanged lines hidden (view full) ---

677 void __iomem *reg = drv_data->ioaddr;
678 u32 clk_div = 0;
679 u8 bits = 0;
680 u32 speed = 0;
681 u32 cr0;
682 u32 cr1;
683 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
684 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
685 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
616
617 /* Get current state information */
618 message = drv_data->cur_msg;
619 transfer = drv_data->cur_transfer;
620 chip = drv_data->cur_chip;
621
622 /* Handle for abort */
623 if (message->state == ERROR_STATE) {

--- 102 unchanged lines hidden (view full) ---

726 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
727 message->spi,
728 bits, &dma_burst,
729 &dma_thresh))
730 dev_warn_ratelimited(&message->spi->dev,
731 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
732 }
733
686
687 /* Get current state information */
688 message = drv_data->cur_msg;
689 transfer = drv_data->cur_transfer;
690 chip = drv_data->cur_chip;
691
692 /* Handle for abort */
693 if (message->state == ERROR_STATE) {

--- 102 unchanged lines hidden (view full) ---

796 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
797 message->spi,
798 bits, &dma_burst,
799 &dma_thresh))
800 dev_warn_ratelimited(&message->spi->dev,
801 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
802 }
803
734 cr0 = clk_div
735 | SSCR0_Motorola
736 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
737 | SSCR0_SSE
738 | (bits > 16 ? SSCR0_EDSS : 0);
804 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
739 }
740
741 message->state = RUNNING_STATE;
742
743 drv_data->dma_mapped = 0;
744 if (pxa2xx_spi_dma_is_possible(drv_data->len))
745 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
746 if (drv_data->dma_mapped) {

--- 20 unchanged lines hidden (view full) ---

767 if (is_lpss_ssp(drv_data)) {
768 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
769 write_SSIRF(chip->lpss_rx_threshold, reg);
770 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
771 write_SSITF(chip->lpss_tx_threshold, reg);
772 }
773
774 /* see if we need to reload the config registers */
805 }
806
807 message->state = RUNNING_STATE;
808
809 drv_data->dma_mapped = 0;
810 if (pxa2xx_spi_dma_is_possible(drv_data->len))
811 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
812 if (drv_data->dma_mapped) {

--- 20 unchanged lines hidden (view full) ---

833 if (is_lpss_ssp(drv_data)) {
834 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
835 write_SSIRF(chip->lpss_rx_threshold, reg);
836 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
837 write_SSITF(chip->lpss_tx_threshold, reg);
838 }
839
840 /* see if we need to reload the config registers */
775 if ((read_SSCR0(reg) != cr0)
776 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
777 (cr1 & SSCR1_CHANGE_MASK)) {
841 if ((read_SSCR0(reg) != cr0) ||
842 (read_SSCR1(reg) & change_mask) != (cr1 & change_mask)) {
778
779 /* stop the SSP, and update the other bits */
780 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
781 if (!pxa25x_ssp_comp(drv_data))
782 write_SSTO(chip->timeout, reg);
783 /* first set CR1 without interrupt and service enables */
843
844 /* stop the SSP, and update the other bits */
845 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
846 if (!pxa25x_ssp_comp(drv_data))
847 write_SSTO(chip->timeout, reg);
848 /* first set CR1 without interrupt and service enables */
784 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
849 write_SSCR1(cr1 & change_mask, reg);
785 /* restart the SSP */
786 write_SSCR0(cr0, reg);
787
788 } else {
789 if (!pxa25x_ssp_comp(drv_data))
790 write_SSTO(chip->timeout, reg);
791 }
792

--- 161 unchanged lines hidden (view full) ---

954 dev_warn(&spi->dev,
955 "in setup: DMA burst size reduced to match bits_per_word\n");
956 }
957 }
958
959 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
960 chip->speed_hz = spi->max_speed_hz;
961
850 /* restart the SSP */
851 write_SSCR0(cr0, reg);
852
853 } else {
854 if (!pxa25x_ssp_comp(drv_data))
855 write_SSTO(chip->timeout, reg);
856 }
857

--- 161 unchanged lines hidden (view full) ---

1019 dev_warn(&spi->dev,
1020 "in setup: DMA burst size reduced to match bits_per_word\n");
1021 }
1022 }
1023
1024 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
1025 chip->speed_hz = spi->max_speed_hz;
1026
962 chip->cr0 = clk_div
963 | SSCR0_Motorola
964 | SSCR0_DataSize(spi->bits_per_word > 16 ?
965 spi->bits_per_word - 16 : spi->bits_per_word)
966 | SSCR0_SSE
967 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1027 chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div,
1028 spi->bits_per_word);
968 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
969 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
970 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
971
972 if (spi->mode & SPI_LOOP)
973 chip->cr1 |= SSCR1_LBM;
974
975 /* NOTE: PXA25x_SSP _could_ use external clocking ... */

--- 381 unchanged lines hidden --- 		1029 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1030 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1031 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1032
1033 if (spi->mode & SPI_LOOP)
1034 chip->cr1 |= SSCR1_LBM;
1035
1036 /* NOTE: PXA25x_SSP _could_ use external clocking ... */

--- 381 unchanged lines hidden ---