spi-pxa2xx.c (2db73d4482da9bd979edee345e95bb3a88441b30) spi-pxa2xx.c (7566bcc76b15186172c4db0414cf30c8a61e4a73)
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

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246 * Perform LPSS SSP specific setup. This function must be called first if
247 * one is going to use LPSS SSP private registers.
248 */
249static void lpss_ssp_setup(struct driver_data *drv_data)
250{
251 unsigned offset = 0x400;
252 u32 value, orig;
253
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

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246 * Perform LPSS SSP specific setup. This function must be called first if
247 * one is going to use LPSS SSP private registers.
248 */
249static void lpss_ssp_setup(struct driver_data *drv_data)
250{
251 unsigned offset = 0x400;
252 u32 value, orig;
253
254 if (!is_lpss_ssp(drv_data))
255 return;
256
257 /*
258 * Perform auto-detection of the LPSS SSP private registers. They
259 * can be either at 1k or 2k offset from the base address.
260 */
261 orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
262
263 /* Test SPI_CS_CONTROL_SW_MODE bit enabling */
264 value = orig | SPI_CS_CONTROL_SW_MODE;

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297 __lpss_ssp_write_priv(drv_data, GENERAL_REG, value);
298 }
299}
300
301static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
302{
303 u32 value;
304
254 /*
255 * Perform auto-detection of the LPSS SSP private registers. They
256 * can be either at 1k or 2k offset from the base address.
257 */
258 orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
259
260 /* Test SPI_CS_CONTROL_SW_MODE bit enabling */
261 value = orig | SPI_CS_CONTROL_SW_MODE;

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294 __lpss_ssp_write_priv(drv_data, GENERAL_REG, value);
295 }
296}
297
298static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
299{
300 u32 value;
301
305 if (!is_lpss_ssp(drv_data))
306 return;
307
308 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
309 if (enable)
310 value &= ~SPI_CS_CONTROL_CS_HIGH;
311 else
312 value |= SPI_CS_CONTROL_CS_HIGH;
313 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
314}
315

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327 return;
328 }
329
330 if (gpio_is_valid(chip->gpio_cs)) {
331 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
332 return;
333 }
334
302 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
303 if (enable)
304 value &= ~SPI_CS_CONTROL_CS_HIGH;
305 else
306 value |= SPI_CS_CONTROL_CS_HIGH;
307 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
308}
309

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321 return;
322 }
323
324 if (gpio_is_valid(chip->gpio_cs)) {
325 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
326 return;
327 }
328
335 lpss_ssp_cs_control(drv_data, true);
329 if (is_lpss_ssp(drv_data))
330 lpss_ssp_cs_control(drv_data, true);
336}
337
338static void cs_deassert(struct driver_data *drv_data)
339{
340 struct chip_data *chip = drv_data->cur_chip;
341
342 if (drv_data->ssp_type == CE4100_SSP)
343 return;
344
345 if (chip->cs_control) {
346 chip->cs_control(PXA2XX_CS_DEASSERT);
347 return;
348 }
349
350 if (gpio_is_valid(chip->gpio_cs)) {
351 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
352 return;
353 }
354
331}
332
333static void cs_deassert(struct driver_data *drv_data)
334{
335 struct chip_data *chip = drv_data->cur_chip;
336
337 if (drv_data->ssp_type == CE4100_SSP)
338 return;
339
340 if (chip->cs_control) {
341 chip->cs_control(PXA2XX_CS_DEASSERT);
342 return;
343 }
344
345 if (gpio_is_valid(chip->gpio_cs)) {
346 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
347 return;
348 }
349
355 lpss_ssp_cs_control(drv_data, false);
350 if (is_lpss_ssp(drv_data))
351 lpss_ssp_cs_control(drv_data, false);
356}
357
358int pxa2xx_spi_flush(struct driver_data *drv_data)
359{
360 unsigned long limit = loops_per_jiffy << 1;
361
362 void __iomem *reg = drv_data->ioaddr;
363

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1410 }
1411
1412 if (!pxa25x_ssp_comp(drv_data))
1413 write_SSTO(0, drv_data->ioaddr);
1414
1415 if (!is_quark_x1000_ssp(drv_data))
1416 write_SSPSP(0, drv_data->ioaddr);
1417
352}
353
354int pxa2xx_spi_flush(struct driver_data *drv_data)
355{
356 unsigned long limit = loops_per_jiffy << 1;
357
358 void __iomem *reg = drv_data->ioaddr;
359

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1406 }
1407
1408 if (!pxa25x_ssp_comp(drv_data))
1409 write_SSTO(0, drv_data->ioaddr);
1410
1411 if (!is_quark_x1000_ssp(drv_data))
1412 write_SSPSP(0, drv_data->ioaddr);
1413
1418 lpss_ssp_setup(drv_data);
1414 if (is_lpss_ssp(drv_data))
1415 lpss_ssp_setup(drv_data);
1419
1420 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1421 (unsigned long)drv_data);
1422
1423 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1424 pm_runtime_use_autosuspend(&pdev->dev);
1425 pm_runtime_set_active(&pdev->dev);
1426 pm_runtime_enable(&pdev->dev);

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1417 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1418 (unsigned long)drv_data);
1419
1420 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1421 pm_runtime_use_autosuspend(&pdev->dev);
1422 pm_runtime_set_active(&pdev->dev);
1423 pm_runtime_enable(&pdev->dev);

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