spi-pxa2xx.c (03e075b38e6cd25267c8d6e2797fa4537ca3348d) spi-pxa2xx.c (07550df04712c88717d2ab6578bb36bbd4305e35)
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

--- 558 unchanged lines hidden (view full) ---

567 dev_err(&drv_data->pdev->dev, "%s\n", msg);
568
569 drv_data->cur_msg->state = ERROR_STATE;
570 tasklet_schedule(&drv_data->pump_transfers);
571}
572
573static void int_transfer_complete(struct driver_data *drv_data)
574{
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

--- 558 unchanged lines hidden (view full) ---

567 dev_err(&drv_data->pdev->dev, "%s\n", msg);
568
569 drv_data->cur_msg->state = ERROR_STATE;
570 tasklet_schedule(&drv_data->pump_transfers);
571}
572
573static void int_transfer_complete(struct driver_data *drv_data)
574{
575 /* Stop SSP */
575 /* Clear and disable interrupts */
576 write_SSSR_CS(drv_data, drv_data->clear_sr);
577 reset_sccr1(drv_data);
578 if (!pxa25x_ssp_comp(drv_data))
579 pxa2xx_spi_write(drv_data, SSTO, 0);
580
581 /* Update total byte transferred return count actual bytes read */
582 drv_data->cur_msg->actual_length += drv_data->len -
583 (drv_data->rx_end - drv_data->rx);

--- 412 unchanged lines hidden (view full) ---

996 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
997 message->spi,
998 bits, &dma_burst,
999 &dma_thresh))
1000 dev_warn_ratelimited(&message->spi->dev,
1001 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1002 }
1003
576 write_SSSR_CS(drv_data, drv_data->clear_sr);
577 reset_sccr1(drv_data);
578 if (!pxa25x_ssp_comp(drv_data))
579 pxa2xx_spi_write(drv_data, SSTO, 0);
580
581 /* Update total byte transferred return count actual bytes read */
582 drv_data->cur_msg->actual_length += drv_data->len -
583 (drv_data->rx_end - drv_data->rx);

--- 412 unchanged lines hidden (view full) ---

996 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
997 message->spi,
998 bits, &dma_burst,
999 &dma_thresh))
1000 dev_warn_ratelimited(&message->spi->dev,
1001 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1002 }
1003
1004 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1005 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1006 if (!pxa25x_ssp_comp(drv_data))
1007 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1008 drv_data->master->max_speed_hz
1009 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1010 chip->enable_dma ? "DMA" : "PIO");
1011 else
1012 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1013 drv_data->master->max_speed_hz / 2
1014 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1015 chip->enable_dma ? "DMA" : "PIO");
1016
1017 message->state = RUNNING_STATE;
1018
1019 drv_data->dma_mapped = 0;
1020 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1021 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
1022 if (drv_data->dma_mapped) {
1023
1024 /* Ensure we have the correct interrupt handler */

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1035 /* Ensure we have the correct interrupt handler */
1036 drv_data->transfer_handler = interrupt_transfer;
1037
1038 /* Clear status */
1039 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1040 write_SSSR_CS(drv_data, drv_data->clear_sr);
1041 }
1042
1004 message->state = RUNNING_STATE;
1005
1006 drv_data->dma_mapped = 0;
1007 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1008 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
1009 if (drv_data->dma_mapped) {
1010
1011 /* Ensure we have the correct interrupt handler */

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1022 /* Ensure we have the correct interrupt handler */
1023 drv_data->transfer_handler = interrupt_transfer;
1024
1025 /* Clear status */
1026 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1027 write_SSSR_CS(drv_data, drv_data->clear_sr);
1028 }
1029
1030 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1031 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1032 if (!pxa25x_ssp_comp(drv_data))
1033 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1034 drv_data->master->max_speed_hz
1035 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1036 drv_data->dma_mapped ? "DMA" : "PIO");
1037 else
1038 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1039 drv_data->master->max_speed_hz / 2
1040 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1041 drv_data->dma_mapped ? "DMA" : "PIO");
1042
1043 if (is_lpss_ssp(drv_data)) {
1044 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1045 != chip->lpss_rx_threshold)
1046 pxa2xx_spi_write(drv_data, SSIRF,
1047 chip->lpss_rx_threshold);
1048 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1049 != chip->lpss_tx_threshold)
1050 pxa2xx_spi_write(drv_data, SSITF,

--- 689 unchanged lines hidden --- 		1043 if (is_lpss_ssp(drv_data)) {
1044 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1045 != chip->lpss_rx_threshold)
1046 pxa2xx_spi_write(drv_data, SSIRF,
1047 chip->lpss_rx_threshold);
1048 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1049 != chip->lpss_tx_threshold)
1050 pxa2xx_spi_write(drv_data, SSITF,

--- 689 unchanged lines hidden ---