spi-davinci.c (048177ce3b3962852fd34a7e04938959271c7e70) spi-davinci.c (ec2a0833e5157fab6cac5f57a49b2f31eb418a39)
1/*
2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

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20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26#include <linux/err.h>
27#include <linux/clk.h>
1/*
2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

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20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28#include <linux/dmaengine.h>
29#include <linux/dma-mapping.h>
28#include <linux/dma-mapping.h>
30#include <linux/edma.h>
31#include <linux/spi/spi.h>
32#include <linux/spi/spi_bitbang.h>
33#include <linux/slab.h>
34
29#include <linux/spi/spi.h>
30#include <linux/spi/spi_bitbang.h>
31#include <linux/slab.h>
32
35#include <mach/spi.h>
33#include <linux/platform_data/spi-davinci.h>
34#include <mach/edma.h>
36
37#define SPI_NO_RESOURCE ((resource_size_t)-1)
38
39#define SPI_MAX_CHIPSELECT 2
40
41#define CS_DEFAULT 0xFF
42
43#define SPIFMT_PHASE_MASK BIT(16)

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109#define SPIFLG 0x10
110#define SPIPC0 0x14
111#define SPIDAT1 0x3c
112#define SPIBUF 0x40
113#define SPIDELAY 0x48
114#define SPIDEF 0x4c
115#define SPIFMT0 0x50
116
35
36#define SPI_NO_RESOURCE ((resource_size_t)-1)
37
38#define SPI_MAX_CHIPSELECT 2
39
40#define CS_DEFAULT 0xFF
41
42#define SPIFMT_PHASE_MASK BIT(16)

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108#define SPIFLG 0x10
109#define SPIPC0 0x14
110#define SPIDAT1 0x3c
111#define SPIBUF 0x40
112#define SPIDELAY 0x48
113#define SPIDEF 0x4c
114#define SPIFMT0 0x50
115
116/* We have 2 DMA channels per CS, one for RX and one for TX */
117struct davinci_spi_dma {
118 int tx_channel;
119 int rx_channel;
120 int dummy_param_slot;
121 enum dma_event_q eventq;
122};
123
117/* SPI Controller driver's private data. */
118struct davinci_spi {
119 struct spi_bitbang bitbang;
120 struct clk *clk;
121
122 u8 version;
123 resource_size_t pbase;
124 void __iomem *base;
125 u32 irq;
126 struct completion done;
127
128 const void *tx;
129 void *rx;
124/* SPI Controller driver's private data. */
125struct davinci_spi {
126 struct spi_bitbang bitbang;
127 struct clk *clk;
128
129 u8 version;
130 resource_size_t pbase;
131 void __iomem *base;
132 u32 irq;
133 struct completion done;
134
135 const void *tx;
136 void *rx;
137#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1)
138 u8 rx_tmp_buf[SPI_TMP_BUFSZ];
130 int rcount;
131 int wcount;
139 int rcount;
140 int wcount;
132
133 struct dma_chan *dma_rx;
134 struct dma_chan *dma_tx;
135 int dma_rx_chnum;
136 int dma_tx_chnum;
137
141 struct davinci_spi_dma dma;
138 struct davinci_spi_platform_data *pdata;
139
140 void (*get_rx)(u32 rx_data, struct davinci_spi *);
141 u32 (*get_tx)(struct davinci_spi *);
142
143 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
144};
145

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487 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
488 iowrite32(spidat1, dspi->base + SPIDAT1);
489 }
490
491out:
492 return errors;
493}
494
142 struct davinci_spi_platform_data *pdata;
143
144 void (*get_rx)(u32 rx_data, struct davinci_spi *);
145 u32 (*get_tx)(struct davinci_spi *);
146
147 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
148};
149

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491 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
492 iowrite32(spidat1, dspi->base + SPIDAT1);
493 }
494
495out:
496 return errors;
497}
498
495static void davinci_spi_dma_rx_callback(void *data)
499static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
496{
500{
497 struct davinci_spi *dspi = (struct davinci_spi *)data;
501 struct davinci_spi *dspi = data;
502 struct davinci_spi_dma *dma = &dspi->dma;
498
503
499 dspi->rcount = 0;
504 edma_stop(lch);
500
505
501 if (!dspi->wcount && !dspi->rcount)
502 complete(&dspi->done);
503}
506 if (status == DMA_COMPLETE) {
507 if (lch == dma->rx_channel)
508 dspi->rcount = 0;
509 if (lch == dma->tx_channel)
510 dspi->wcount = 0;
511 }
504
512
505static void davinci_spi_dma_tx_callback(void *data)
506{
507 struct davinci_spi *dspi = (struct davinci_spi *)data;
508
509 dspi->wcount = 0;
510
511 if (!dspi->wcount && !dspi->rcount)
513 if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
512 complete(&dspi->done);
513}
514
515/**
516 * davinci_spi_bufs - functions which will handle transfer data
517 * @spi: spi device on which data transfer to be done
518 * @t: spi transfer in which transfer info is filled
519 *
520 * This function will put data to be transferred into data register
521 * of SPI controller and then wait until the completion will be marked
522 * by the IRQ Handler.
523 */
524static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
525{
526 struct davinci_spi *dspi;
514 complete(&dspi->done);
515}
516
517/**
518 * davinci_spi_bufs - functions which will handle transfer data
519 * @spi: spi device on which data transfer to be done
520 * @t: spi transfer in which transfer info is filled
521 *
522 * This function will put data to be transferred into data register
523 * of SPI controller and then wait until the completion will be marked
524 * by the IRQ Handler.
525 */
526static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
527{
528 struct davinci_spi *dspi;
527 int data_type, ret = -ENOMEM;
529 int data_type, ret;
528 u32 tx_data, spidat1;
529 u32 errors = 0;
530 struct davinci_spi_config *spicfg;
531 struct davinci_spi_platform_data *pdata;
532 unsigned uninitialized_var(rx_buf_count);
530 u32 tx_data, spidat1;
531 u32 errors = 0;
532 struct davinci_spi_config *spicfg;
533 struct davinci_spi_platform_data *pdata;
534 unsigned uninitialized_var(rx_buf_count);
533 void *dummy_buf = NULL;
534 struct scatterlist sg_rx, sg_tx;
535 struct device *sdev;
535
536 dspi = spi_master_get_devdata(spi->master);
537 pdata = dspi->pdata;
538 spicfg = (struct davinci_spi_config *)spi->controller_data;
539 if (!spicfg)
540 spicfg = &davinci_spi_default_cfg;
536
537 dspi = spi_master_get_devdata(spi->master);
538 pdata = dspi->pdata;
539 spicfg = (struct davinci_spi_config *)spi->controller_data;
540 if (!spicfg)
541 spicfg = &davinci_spi_default_cfg;
542 sdev = dspi->bitbang.master->dev.parent;
541
542 /* convert len to words based on bits_per_word */
543 data_type = dspi->bytes_per_word[spi->chip_select];
544
545 dspi->tx = t->tx_buf;
546 dspi->rx = t->rx_buf;
547 dspi->wcount = t->len / data_type;
548 dspi->rcount = dspi->wcount;

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560 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
561 /* start the transfer */
562 dspi->wcount--;
563 tx_data = dspi->get_tx(dspi);
564 spidat1 &= 0xFFFF0000;
565 spidat1 |= tx_data & 0xFFFF;
566 iowrite32(spidat1, dspi->base + SPIDAT1);
567 } else {
543
544 /* convert len to words based on bits_per_word */
545 data_type = dspi->bytes_per_word[spi->chip_select];
546
547 dspi->tx = t->tx_buf;
548 dspi->rx = t->rx_buf;
549 dspi->wcount = t->len / data_type;
550 dspi->rcount = dspi->wcount;

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562 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
563 /* start the transfer */
564 dspi->wcount--;
565 tx_data = dspi->get_tx(dspi);
566 spidat1 &= 0xFFFF0000;
567 spidat1 |= tx_data & 0xFFFF;
568 iowrite32(spidat1, dspi->base + SPIDAT1);
569 } else {
568 struct dma_slave_config dma_rx_conf = {
569 .direction = DMA_DEV_TO_MEM,
570 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
571 .src_addr_width = data_type,
572 .src_maxburst = 1,
573 };
574 struct dma_slave_config dma_tx_conf = {
575 .direction = DMA_MEM_TO_DEV,
576 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
577 .dst_addr_width = data_type,
578 .dst_maxburst = 1,
579 };
580 struct dma_async_tx_descriptor *rxdesc;
581 struct dma_async_tx_descriptor *txdesc;
582 void *buf;
570 struct davinci_spi_dma *dma;
571 unsigned long tx_reg, rx_reg;
572 struct edmacc_param param;
573 void *rx_buf;
574 int b, c;
583
575
584 dummy_buf = kzalloc(t->len, GFP_KERNEL);
585 if (!dummy_buf)
586 goto err_alloc_dummy_buf;
576 dma = &dspi->dma;
587
577
588 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
589 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
578 tx_reg = (unsigned long)dspi->pbase + SPIDAT1;
579 rx_reg = (unsigned long)dspi->pbase + SPIBUF;
590
580
591 sg_init_table(&sg_rx, 1);
592 if (!t->rx_buf)
593 buf = dummy_buf;
594 else
595 buf = t->rx_buf;
596 t->rx_dma = dma_map_single(&spi->dev, buf,
597 t->len, DMA_FROM_DEVICE);
598 if (!t->rx_dma) {
599 ret = -EFAULT;
600 goto err_rx_map;
581 /*
582 * Transmit DMA setup
583 *
584 * If there is transmit data, map the transmit buffer, set it
585 * as the source of data and set the source B index to data
586 * size. If there is no transmit data, set the transmit register
587 * as the source of data, and set the source B index to zero.
588 *
589 * The destination is always the transmit register itself. And
590 * the destination never increments.
591 */
592
593 if (t->tx_buf) {
594 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
595 t->len, DMA_TO_DEVICE);
596 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
597 dev_dbg(sdev, "Unable to DMA map %d bytes"
598 "TX buffer\n", t->len);
599 return -ENOMEM;
600 }
601 }
601 }
602 sg_dma_address(&sg_rx) = t->rx_dma;
603 sg_dma_len(&sg_rx) = t->len;
604
602
605 sg_init_table(&sg_tx, 1);
606 if (!t->tx_buf)
607 buf = dummy_buf;
603 /*
604 * If number of words is greater than 65535, then we need
605 * to configure a 3 dimension transfer. Use the BCNTRLD
606 * feature to allow for transfers that aren't even multiples
607 * of 65535 (or any other possible b size) by first transferring
608 * the remainder amount then grabbing the next N blocks of
609 * 65535 words.
610 */
611
612 c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */
613 b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */
614 if (b)
615 c++;
608 else
616 else
609 buf = (void *)t->tx_buf;
610 t->tx_dma = dma_map_single(&spi->dev, buf,
611 t->len, DMA_FROM_DEVICE);
612 if (!t->tx_dma) {
613 ret = -EFAULT;
614 goto err_tx_map;
615 }
616 sg_dma_address(&sg_tx) = t->tx_dma;
617 sg_dma_len(&sg_tx) = t->len;
617 b = SZ_64K - 1;
618
618
619 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
620 &sg_rx, 1, DMA_DEV_TO_MEM,
621 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
622 if (!rxdesc)
623 goto err_desc;
619 param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
620 param.src = t->tx_buf ? t->tx_dma : tx_reg;
621 param.a_b_cnt = b << 16 | data_type;
622 param.dst = tx_reg;
623 param.src_dst_bidx = t->tx_buf ? data_type : 0;
624 param.link_bcntrld = 0xffffffff;
625 param.src_dst_cidx = t->tx_buf ? data_type : 0;
626 param.ccnt = c;
627 edma_write_slot(dma->tx_channel, &param);
628 edma_link(dma->tx_channel, dma->dummy_param_slot);
624
629
625 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
626 &sg_tx, 1, DMA_MEM_TO_DEV,
627 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
628 if (!txdesc)
629 goto err_desc;
630 /*
631 * Receive DMA setup
632 *
633 * If there is receive buffer, use it to receive data. If there
634 * is none provided, use a temporary receive buffer. Set the
635 * destination B index to 0 so effectively only one byte is used
636 * in the temporary buffer (address does not increment).
637 *
638 * The source of receive data is the receive data register. The
639 * source address never increments.
640 */
630
641
631 rxdesc->callback = davinci_spi_dma_rx_callback;
632 rxdesc->callback_param = (void *)dspi;
633 txdesc->callback = davinci_spi_dma_tx_callback;
634 txdesc->callback_param = (void *)dspi;
642 if (t->rx_buf) {
643 rx_buf = t->rx_buf;
644 rx_buf_count = t->len;
645 } else {
646 rx_buf = dspi->rx_tmp_buf;
647 rx_buf_count = sizeof(dspi->rx_tmp_buf);
648 }
635
649
650 t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
651 DMA_FROM_DEVICE);
652 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
653 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
654 rx_buf_count);
655 if (t->tx_buf)
656 dma_unmap_single(&spi->dev, t->tx_dma, t->len,
657 DMA_TO_DEVICE);
658 return -ENOMEM;
659 }
660
661 param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
662 param.src = rx_reg;
663 param.a_b_cnt = b << 16 | data_type;
664 param.dst = t->rx_dma;
665 param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
666 param.link_bcntrld = 0xffffffff;
667 param.src_dst_cidx = (t->rx_buf ? data_type : 0) << 16;
668 param.ccnt = c;
669 edma_write_slot(dma->rx_channel, &param);
670
636 if (pdata->cshold_bug)
637 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
638
671 if (pdata->cshold_bug)
672 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
673
639 dmaengine_submit(rxdesc);
640 dmaengine_submit(txdesc);
641
642 dma_async_issue_pending(dspi->dma_rx);
643 dma_async_issue_pending(dspi->dma_tx);
644
674 edma_start(dma->rx_channel);
675 edma_start(dma->tx_channel);
645 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
646 }
647
648 /* Wait for the transfer to complete */
649 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
650 wait_for_completion_interruptible(&(dspi->done));
651 } else {
652 while (dspi->rcount > 0 || dspi->wcount > 0) {
653 errors = davinci_spi_process_events(dspi);
654 if (errors)
655 break;
656 cpu_relax();
657 }
658 }
659
660 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
661 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
676 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
677 }
678
679 /* Wait for the transfer to complete */
680 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
681 wait_for_completion_interruptible(&(dspi->done));
682 } else {
683 while (dspi->rcount > 0 || dspi->wcount > 0) {
684 errors = davinci_spi_process_events(dspi);
685 if (errors)
686 break;
687 cpu_relax();
688 }
689 }
690
691 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
692 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
662 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
663
693
664 dma_unmap_single(&spi->dev, t->rx_dma,
665 t->len, DMA_FROM_DEVICE);
666 dma_unmap_single(&spi->dev, t->tx_dma,
667 t->len, DMA_TO_DEVICE);
668 kfree(dummy_buf);
694 if (t->tx_buf)
695 dma_unmap_single(&spi->dev, t->tx_dma, t->len,
696 DMA_TO_DEVICE);
697
698 dma_unmap_single(&spi->dev, t->rx_dma, rx_buf_count,
699 DMA_FROM_DEVICE);
700
701 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
669 }
670
671 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
672 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
673
674 /*
675 * Check for bit error, desync error,parity error,timeout error and
676 * receive overflow errors
677 */
678 if (errors) {
679 ret = davinci_spi_check_error(dspi, errors);
680 WARN(!ret, "%s: error reported but no error found!\n",
681 dev_name(&spi->dev));
682 return ret;
683 }
684
685 if (dspi->rcount != 0 || dspi->wcount != 0) {
702 }
703
704 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
705 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
706
707 /*
708 * Check for bit error, desync error,parity error,timeout error and
709 * receive overflow errors
710 */
711 if (errors) {
712 ret = davinci_spi_check_error(dspi, errors);
713 WARN(!ret, "%s: error reported but no error found!\n",
714 dev_name(&spi->dev));
715 return ret;
716 }
717
718 if (dspi->rcount != 0 || dspi->wcount != 0) {
686 dev_err(&spi->dev, "SPI data transfer error\n");
719 dev_err(sdev, "SPI data transfer error\n");
687 return -EIO;
688 }
689
690 return t->len;
720 return -EIO;
721 }
722
723 return t->len;
691
692err_desc:
693 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
694err_tx_map:
695 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
696err_rx_map:
697 kfree(dummy_buf);
698err_alloc_dummy_buf:
699 return ret;
700}
701
702/**
703 * davinci_spi_irq - Interrupt handler for SPI Master Controller
704 * @irq: IRQ number for this SPI Master
705 * @context_data: structure for SPI Master controller davinci_spi
706 *
707 * ISR will determine that interrupt arrives either for READ or WRITE command.

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722 if ((!dspi->rcount && !dspi->wcount) || status)
723 complete(&dspi->done);
724
725 return IRQ_HANDLED;
726}
727
728static int davinci_spi_request_dma(struct davinci_spi *dspi)
729{
724}
725
726/**
727 * davinci_spi_irq - Interrupt handler for SPI Master Controller
728 * @irq: IRQ number for this SPI Master
729 * @context_data: structure for SPI Master controller davinci_spi
730 *
731 * ISR will determine that interrupt arrives either for READ or WRITE command.

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746 if ((!dspi->rcount && !dspi->wcount) || status)
747 complete(&dspi->done);
748
749 return IRQ_HANDLED;
750}
751
752static int davinci_spi_request_dma(struct davinci_spi *dspi)
753{
730 dma_cap_mask_t mask;
731 struct device *sdev = dspi->bitbang.master->dev.parent;
732 int r;
754 int r;
755 struct davinci_spi_dma *dma = &dspi->dma;
733
756
734 dma_cap_zero(mask);
735 dma_cap_set(DMA_SLAVE, mask);
736
737 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
738 &dspi->dma_rx_chnum);
739 if (!dspi->dma_rx) {
740 dev_err(sdev, "request RX DMA channel failed\n");
741 r = -ENODEV;
757 r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
758 dma->eventq);
759 if (r < 0) {
760 pr_err("Unable to request DMA channel for SPI RX\n");
761 r = -EAGAIN;
742 goto rx_dma_failed;
743 }
744
762 goto rx_dma_failed;
763 }
764
745 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
746 &dspi->dma_tx_chnum);
747 if (!dspi->dma_tx) {
748 dev_err(sdev, "request TX DMA channel failed\n");
749 r = -ENODEV;
765 r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
766 dma->eventq);
767 if (r < 0) {
768 pr_err("Unable to request DMA channel for SPI TX\n");
769 r = -EAGAIN;
750 goto tx_dma_failed;
751 }
752
770 goto tx_dma_failed;
771 }
772
753 return 0;
773 r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
774 if (r < 0) {
775 pr_err("Unable to request SPI TX DMA param slot\n");
776 r = -EAGAIN;
777 goto param_failed;
778 }
779 dma->dummy_param_slot = r;
780 edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
754
781
782 return 0;
783param_failed:
784 edma_free_channel(dma->tx_channel);
755tx_dma_failed:
785tx_dma_failed:
756 dma_release_channel(dspi->dma_rx);
786 edma_free_channel(dma->rx_channel);
757rx_dma_failed:
758 return r;
759}
760
761/**
762 * davinci_spi_probe - probe function for SPI Master Controller
763 * @pdev: platform_device structure which contains plateform specific data
764 *

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863 dma_rx_chan = r->start;
864 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
865 if (r)
866 dma_tx_chan = r->start;
867
868 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
869 if (dma_rx_chan != SPI_NO_RESOURCE &&
870 dma_tx_chan != SPI_NO_RESOURCE) {
787rx_dma_failed:
788 return r;
789}
790
791/**
792 * davinci_spi_probe - probe function for SPI Master Controller
793 * @pdev: platform_device structure which contains plateform specific data
794 *

--- 98 unchanged lines hidden (view full) ---

893 dma_rx_chan = r->start;
894 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
895 if (r)
896 dma_tx_chan = r->start;
897
898 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
899 if (dma_rx_chan != SPI_NO_RESOURCE &&
900 dma_tx_chan != SPI_NO_RESOURCE) {
871 dspi->dma_rx_chnum = dma_rx_chan;
872 dspi->dma_tx_chnum = dma_tx_chan;
901 dspi->dma.rx_channel = dma_rx_chan;
902 dspi->dma.tx_channel = dma_tx_chan;
903 dspi->dma.eventq = pdata->dma_event_q;
873
874 ret = davinci_spi_request_dma(dspi);
875 if (ret)
876 goto free_clk;
877
878 dev_info(&pdev->dev, "DMA: supported\n");
879 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
880 "event queue: %d\n", dma_rx_chan, dma_tx_chan,

--- 38 unchanged lines hidden (view full) ---

919 if (ret)
920 goto free_dma;
921
922 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
923
924 return ret;
925
926free_dma:
904
905 ret = davinci_spi_request_dma(dspi);
906 if (ret)
907 goto free_clk;
908
909 dev_info(&pdev->dev, "DMA: supported\n");
910 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
911 "event queue: %d\n", dma_rx_chan, dma_tx_chan,

--- 38 unchanged lines hidden (view full) ---

950 if (ret)
951 goto free_dma;
952
953 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
954
955 return ret;
956
957free_dma:
927 dma_release_channel(dspi->dma_rx);
928 dma_release_channel(dspi->dma_tx);
958 edma_free_channel(dspi->dma.tx_channel);
959 edma_free_channel(dspi->dma.rx_channel);
960 edma_free_slot(dspi->dma.dummy_param_slot);
929free_clk:
930 clk_disable(dspi->clk);
931 clk_put(dspi->clk);
932put_master:
933 spi_master_put(master);
934irq_free:
935 free_irq(dspi->irq, dspi);
936unmap_io:

--- 52 unchanged lines hidden --- 		961free_clk:
962 clk_disable(dspi->clk);
963 clk_put(dspi->clk);
964put_master:
965 spi_master_put(master);
966irq_free:
967 free_irq(dspi->irq, dspi);
968unmap_io:

--- 52 unchanged lines hidden ---