mtk-mmsys.c (ce15e7faa2fc5494abe72e1ce6f7698a7834e986) mtk-mmsys.c (440147639ac79f699a4eb9811d0bc39d3cc815f4)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 */
6
7#include <linux/device.h>
8#include <linux/io.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include <linux/soc/mediatek/mtk-mmsys.h>
12
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 */
6
7#include <linux/device.h>
8#include <linux/io.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include <linux/soc/mediatek/mtk-mmsys.h>
12
13#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
14#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
15#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
16#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
17#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
18#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
19#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
20#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
21#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
22#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
23#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
24#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
25#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
26#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
13#include "mtk-mmsys.h"
27
14
28#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
29#define DISP_REG_CONFIG_OUT_SEL 0x04c
30#define DISP_REG_CONFIG_DSI_SEL 0x050
31#define DISP_REG_CONFIG_DPI_SEL 0x064
32
33#define OVL0_MOUT_EN_COLOR0 0x1
34#define OD_MOUT_EN_RDMA0 0x1
35#define OD1_MOUT_EN_RDMA1 BIT(16)
36#define UFOE_MOUT_EN_DSI0 0x1
37#define COLOR0_SEL_IN_OVL0 0x1
38#define OVL1_MOUT_EN_COLOR1 0x1
39#define GAMMA_MOUT_EN_RDMA1 0x1
40#define RDMA0_SOUT_DPI0 0x2
41#define RDMA0_SOUT_DPI1 0x3
42#define RDMA0_SOUT_DSI1 0x1
43#define RDMA0_SOUT_DSI2 0x4
44#define RDMA0_SOUT_DSI3 0x5
45#define RDMA1_SOUT_DPI0 0x2
46#define RDMA1_SOUT_DPI1 0x3
47#define RDMA1_SOUT_DSI1 0x1
48#define RDMA1_SOUT_DSI2 0x4
49#define RDMA1_SOUT_DSI3 0x5
50#define RDMA2_SOUT_DPI0 0x2
51#define RDMA2_SOUT_DPI1 0x3
52#define RDMA2_SOUT_DSI1 0x1
53#define RDMA2_SOUT_DSI2 0x4
54#define RDMA2_SOUT_DSI3 0x5
55#define DPI0_SEL_IN_RDMA1 0x1
56#define DPI0_SEL_IN_RDMA2 0x3
57#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
58#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
59#define DSI0_SEL_IN_RDMA1 0x1
60#define DSI0_SEL_IN_RDMA2 0x4
61#define DSI1_SEL_IN_RDMA1 0x1
62#define DSI1_SEL_IN_RDMA2 0x4
63#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
64#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
65#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
66#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
67#define COLOR1_SEL_IN_OVL1 0x1
68
69#define OVL_MOUT_EN_RDMA 0x1
70#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
71#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
72#define DSI_SEL_IN_BLS 0x0
73#define DPI_SEL_IN_BLS 0x0
74#define DSI_SEL_IN_RDMA 0x1
75
76struct mtk_mmsys_driver_data {
77 const char *clk_driver;
78};
79
80static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
81 .clk_driver = "clk-mt2701-mm",
15static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
16 .clk_driver = "clk-mt2701-mm",
17 .routes = mmsys_default_routing_table,
18 .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
82};
83
84static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
85 .clk_driver = "clk-mt2712-mm",
19};
20
21static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
22 .clk_driver = "clk-mt2712-mm",
23 .routes = mmsys_default_routing_table,
24 .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
86};
87
88static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
89 .clk_driver = "clk-mt6779-mm",
90};
91
92static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
93 .clk_driver = "clk-mt6797-mm",
94};
95
96static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
97 .clk_driver = "clk-mt8173-mm",
25};
26
27static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
28 .clk_driver = "clk-mt6779-mm",
29};
30
31static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
32 .clk_driver = "clk-mt6797-mm",
33};
34
35static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
36 .clk_driver = "clk-mt8173-mm",
37 .routes = mmsys_default_routing_table,
38 .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
98};
99
100static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
101 .clk_driver = "clk-mt8183-mm",
102};
103
104struct mtk_mmsys {
105 void __iomem *regs;
106 const struct mtk_mmsys_driver_data *data;
107};
108
39};
40
41static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
42 .clk_driver = "clk-mt8183-mm",
43};
44
45struct mtk_mmsys {
46 void __iomem *regs;
47 const struct mtk_mmsys_driver_data *data;
48};
49
109static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
110 enum mtk_ddp_comp_id next,
111 unsigned int *addr)
112{
113 unsigned int value;
114
115 if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
116 *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
117 value = OVL0_MOUT_EN_COLOR0;
118 } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
119 *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
120 value = OVL_MOUT_EN_RDMA;
121 } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
122 *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
123 value = OD_MOUT_EN_RDMA0;
124 } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
125 *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
126 value = UFOE_MOUT_EN_DSI0;
127 } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
128 *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
129 value = OVL1_MOUT_EN_COLOR1;
130 } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
131 *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
132 value = GAMMA_MOUT_EN_RDMA1;
133 } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
134 *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
135 value = OD1_MOUT_EN_RDMA1;
136 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
137 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
138 value = RDMA0_SOUT_DPI0;
139 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
140 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
141 value = RDMA0_SOUT_DPI1;
142 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
143 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
144 value = RDMA0_SOUT_DSI1;
145 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
146 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
147 value = RDMA0_SOUT_DSI2;
148 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
149 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
150 value = RDMA0_SOUT_DSI3;
151 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
152 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
153 value = RDMA1_SOUT_DSI1;
154 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
155 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
156 value = RDMA1_SOUT_DSI2;
157 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
158 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
159 value = RDMA1_SOUT_DSI3;
160 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
161 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
162 value = RDMA1_SOUT_DPI0;
163 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
164 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
165 value = RDMA1_SOUT_DPI1;
166 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
167 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
168 value = RDMA2_SOUT_DPI0;
169 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
170 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
171 value = RDMA2_SOUT_DPI1;
172 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
173 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
174 value = RDMA2_SOUT_DSI1;
175 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
176 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
177 value = RDMA2_SOUT_DSI2;
178 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
179 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
180 value = RDMA2_SOUT_DSI3;
181 } else {
182 value = 0;
183 }
184
185 return value;
186}
187
188static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
189 enum mtk_ddp_comp_id next,
190 unsigned int *addr)
191{
192 unsigned int value;
193
194 if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
195 *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
196 value = COLOR0_SEL_IN_OVL0;
197 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
198 *addr = DISP_REG_CONFIG_DPI_SEL_IN;
199 value = DPI0_SEL_IN_RDMA1;
200 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
201 *addr = DISP_REG_CONFIG_DPI_SEL_IN;
202 value = DPI1_SEL_IN_RDMA1;
203 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
204 *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
205 value = DSI0_SEL_IN_RDMA1;
206 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
207 *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
208 value = DSI1_SEL_IN_RDMA1;
209 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
210 *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
211 value = DSI2_SEL_IN_RDMA1;
212 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
213 *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
214 value = DSI3_SEL_IN_RDMA1;
215 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
216 *addr = DISP_REG_CONFIG_DPI_SEL_IN;
217 value = DPI0_SEL_IN_RDMA2;
218 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
219 *addr = DISP_REG_CONFIG_DPI_SEL_IN;
220 value = DPI1_SEL_IN_RDMA2;
221 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
222 *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
223 value = DSI0_SEL_IN_RDMA2;
224 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
225 *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
226 value = DSI1_SEL_IN_RDMA2;
227 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
228 *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
229 value = DSI2_SEL_IN_RDMA2;
230 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
231 *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
232 value = DSI3_SEL_IN_RDMA2;
233 } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
234 *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
235 value = COLOR1_SEL_IN_OVL1;
236 } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
237 *addr = DISP_REG_CONFIG_DSI_SEL;
238 value = DSI_SEL_IN_BLS;
239 } else {
240 value = 0;
241 }
242
243 return value;
244}
245
246static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
247 enum mtk_ddp_comp_id cur,
248 enum mtk_ddp_comp_id next)
249{
250 if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
251 writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
252 config_regs + DISP_REG_CONFIG_OUT_SEL);
253 } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
254 writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
255 config_regs + DISP_REG_CONFIG_OUT_SEL);
256 writel_relaxed(DSI_SEL_IN_RDMA,
257 config_regs + DISP_REG_CONFIG_DSI_SEL);
258 writel_relaxed(DPI_SEL_IN_BLS,
259 config_regs + DISP_REG_CONFIG_DPI_SEL);
260 }
261}
262
263void mtk_mmsys_ddp_connect(struct device *dev,
264 enum mtk_ddp_comp_id cur,
265 enum mtk_ddp_comp_id next)
266{
267 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
50void mtk_mmsys_ddp_connect(struct device *dev,
51 enum mtk_ddp_comp_id cur,
52 enum mtk_ddp_comp_id next)
53{
54 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
268 unsigned int addr, value, reg;
55 const struct mtk_mmsys_routes *routes = mmsys->data->routes;
56 u32 reg;
57 int i;
269
58
270 value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
271 if (value) {
272 reg = readl_relaxed(mmsys->regs + addr) | value;
273 writel_relaxed(reg, mmsys->regs + addr);
274 }
275
276 mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
277
278 value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
279 if (value) {
280 reg = readl_relaxed(mmsys->regs + addr) | value;
281 writel_relaxed(reg, mmsys->regs + addr);
282 }
59 for (i = 0; i < mmsys->data->num_routes; i++)
60 if (cur == routes[i].from_comp && next == routes[i].to_comp) {
61 reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val;
62 writel_relaxed(reg, mmsys->regs + routes[i].addr);
63 }
283}
284EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
285
286void mtk_mmsys_ddp_disconnect(struct device *dev,
287 enum mtk_ddp_comp_id cur,
288 enum mtk_ddp_comp_id next)
289{
290 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
64}
65EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
66
67void mtk_mmsys_ddp_disconnect(struct device *dev,
68 enum mtk_ddp_comp_id cur,
69 enum mtk_ddp_comp_id next)
70{
71 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
291 unsigned int addr, value, reg;
72 const struct mtk_mmsys_routes *routes = mmsys->data->routes;
73 u32 reg;
74 int i;
292
75
293 value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
294 if (value) {
295 reg = readl_relaxed(mmsys->regs + addr) & ~value;
296 writel_relaxed(reg, mmsys->regs + addr);
297 }
298
299 value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
300 if (value) {
301 reg = readl_relaxed(mmsys->regs + addr) & ~value;
302 writel_relaxed(reg, mmsys->regs + addr);
303 }
76 for (i = 0; i < mmsys->data->num_routes; i++)
77 if (cur == routes[i].from_comp && next == routes[i].to_comp) {
78 reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val;
79 writel_relaxed(reg, mmsys->regs + routes[i].addr);
80 }
304}
305EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
306
307static int mtk_mmsys_probe(struct platform_device *pdev)
308{
309 struct device *dev = &pdev->dev;
310 struct platform_device *clks;
311 struct platform_device *drm;

--- 69 unchanged lines hidden --- 		81}
82EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
83
84static int mtk_mmsys_probe(struct platform_device *pdev)
85{
86 struct device *dev = &pdev->dev;
87 struct platform_device *clks;
88 struct platform_device *drm;

--- 69 unchanged lines hidden ---