host.c (4e4dca3de9658f364d34924e072f2b64e5c3d267) host.c (dc00c8b6940aa10ab1ce6a4d10b1bfe7b848781b)
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *

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1881#define AFE_REGISTER_WRITE_DELAY 10
1882
1883/* Initialize the AFE for this phy index. We need to read the AFE setup from
1884 * the OEM parameters
1885 */
1886static void sci_controller_afe_initialization(struct isci_host *ihost)
1887{
1888 const struct sci_oem_params *oem = &ihost->oem_parameters;
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *

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1881#define AFE_REGISTER_WRITE_DELAY 10
1882
1883/* Initialize the AFE for this phy index. We need to read the AFE setup from
1884 * the OEM parameters
1885 */
1886static void sci_controller_afe_initialization(struct isci_host *ihost)
1887{
1888 const struct sci_oem_params *oem = &ihost->oem_parameters;
1889 struct pci_dev *pdev = ihost->pdev;
1889 u32 afe_status;
1890 u32 phy_id;
1891
1892 /* Clear DFX Status registers */
1893 writel(0x0081000f, &ihost->scu_registers->afe.afe_dfx_master_control0);
1894 udelay(AFE_REGISTER_WRITE_DELAY);
1895
1890 u32 afe_status;
1891 u32 phy_id;
1892
1893 /* Clear DFX Status registers */
1894 writel(0x0081000f, &ihost->scu_registers->afe.afe_dfx_master_control0);
1895 udelay(AFE_REGISTER_WRITE_DELAY);
1896
1896 if (is_b0()) {
1897 if (is_b0(pdev)) {
1897 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1898 * Timer, PM Stagger Timer */
1899 writel(0x0007BFFF, &ihost->scu_registers->afe.afe_pmsn_master_control2);
1900 udelay(AFE_REGISTER_WRITE_DELAY);
1901 }
1902
1903 /* Configure bias currents to normal */
1898 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1899 * Timer, PM Stagger Timer */
1900 writel(0x0007BFFF, &ihost->scu_registers->afe.afe_pmsn_master_control2);
1901 udelay(AFE_REGISTER_WRITE_DELAY);
1902 }
1903
1904 /* Configure bias currents to normal */
1904 if (is_a0())
1905 writel(0x00005500, &ihost->scu_registers->afe.afe_bias_control);
1906 else if (is_a2())
1905 if (is_a2(pdev))
1907 writel(0x00005A00, &ihost->scu_registers->afe.afe_bias_control);
1906 writel(0x00005A00, &ihost->scu_registers->afe.afe_bias_control);
1908 else if (is_b0() || is_c0())
1907 else if (is_b0(pdev) || is_c0(pdev))
1909 writel(0x00005F00, &ihost->scu_registers->afe.afe_bias_control);
1910
1911 udelay(AFE_REGISTER_WRITE_DELAY);
1912
1913 /* Enable PLL */
1908 writel(0x00005F00, &ihost->scu_registers->afe.afe_bias_control);
1909
1910 udelay(AFE_REGISTER_WRITE_DELAY);
1911
1912 /* Enable PLL */
1914 if (is_b0() || is_c0())
1913 if (is_b0(pdev) || is_c0(pdev))
1915 writel(0x80040A08, &ihost->scu_registers->afe.afe_pll_control0);
1916 else
1917 writel(0x80040908, &ihost->scu_registers->afe.afe_pll_control0);
1918
1919 udelay(AFE_REGISTER_WRITE_DELAY);
1920
1921 /* Wait for the PLL to lock */
1922 do {
1923 afe_status = readl(&ihost->scu_registers->afe.afe_common_block_status);
1924 udelay(AFE_REGISTER_WRITE_DELAY);
1925 } while ((afe_status & 0x00001000) == 0);
1926
1914 writel(0x80040A08, &ihost->scu_registers->afe.afe_pll_control0);
1915 else
1916 writel(0x80040908, &ihost->scu_registers->afe.afe_pll_control0);
1917
1918 udelay(AFE_REGISTER_WRITE_DELAY);
1919
1920 /* Wait for the PLL to lock */
1921 do {
1922 afe_status = readl(&ihost->scu_registers->afe.afe_common_block_status);
1923 udelay(AFE_REGISTER_WRITE_DELAY);
1924 } while ((afe_status & 0x00001000) == 0);
1925
1927 if (is_a0() || is_a2()) {
1926 if (is_a2(pdev)) {
1928 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
1929 writel(0x7bcc96ad, &ihost->scu_registers->afe.afe_pmsn_master_control0);
1930 udelay(AFE_REGISTER_WRITE_DELAY);
1931 }
1932
1933 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
1934 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
1935
1927 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
1928 writel(0x7bcc96ad, &ihost->scu_registers->afe.afe_pmsn_master_control0);
1929 udelay(AFE_REGISTER_WRITE_DELAY);
1930 }
1931
1932 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
1933 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
1934
1936 if (is_b0()) {
1935 if (is_b0(pdev)) {
1937 /* Configure transmitter SSC parameters */
1938 writel(0x00030000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
1939 udelay(AFE_REGISTER_WRITE_DELAY);
1936 /* Configure transmitter SSC parameters */
1937 writel(0x00030000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
1938 udelay(AFE_REGISTER_WRITE_DELAY);
1940 } else if (is_c0()) {
1939 } else if (is_c0(pdev)) {
1941 /* Configure transmitter SSC parameters */
1942 writel(0x0003000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
1943 udelay(AFE_REGISTER_WRITE_DELAY);
1944
1945 /*
1946 * All defaults, except the Receive Word Alignament/Comma Detect
1947 * Enable....(0xe800) */
1948 writel(0x00004500, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);

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1956
1957 writel(0x0050100F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1);
1958 udelay(AFE_REGISTER_WRITE_DELAY);
1959 }
1960
1961 /*
1962 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
1963 * & increase TX int & ext bias 20%....(0xe85c) */
1940 /* Configure transmitter SSC parameters */
1941 writel(0x0003000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
1942 udelay(AFE_REGISTER_WRITE_DELAY);
1943
1944 /*
1945 * All defaults, except the Receive Word Alignament/Comma Detect
1946 * Enable....(0xe800) */
1947 writel(0x00004500, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);

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1955
1956 writel(0x0050100F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1);
1957 udelay(AFE_REGISTER_WRITE_DELAY);
1958 }
1959
1960 /*
1961 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
1962 * & increase TX int & ext bias 20%....(0xe85c) */
1964 if (is_a0())
1965 writel(0x000003D4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1966 else if (is_a2())
1963 if (is_a2(pdev))
1967 writel(0x000003F0, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1964 writel(0x000003F0, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1968 else if (is_b0()) {
1965 else if (is_b0(pdev)) {
1969 /* Power down TX and RX (PWRDNTX and PWRDNRX) */
1970 writel(0x000003D7, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1971 udelay(AFE_REGISTER_WRITE_DELAY);
1972
1973 /*
1974 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
1975 * & increase TX int & ext bias 20%....(0xe85c) */
1976 writel(0x000003D4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1977 } else {
1978 writel(0x000001E7, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1979 udelay(AFE_REGISTER_WRITE_DELAY);
1980
1981 /*
1982 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
1983 * & increase TX int & ext bias 20%....(0xe85c) */
1984 writel(0x000001E4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1985 }
1986 udelay(AFE_REGISTER_WRITE_DELAY);
1987
1966 /* Power down TX and RX (PWRDNTX and PWRDNRX) */
1967 writel(0x000003D7, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1968 udelay(AFE_REGISTER_WRITE_DELAY);
1969
1970 /*
1971 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
1972 * & increase TX int & ext bias 20%....(0xe85c) */
1973 writel(0x000003D4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1974 } else {
1975 writel(0x000001E7, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1976 udelay(AFE_REGISTER_WRITE_DELAY);
1977
1978 /*
1979 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
1980 * & increase TX int & ext bias 20%....(0xe85c) */
1981 writel(0x000001E4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
1982 }
1983 udelay(AFE_REGISTER_WRITE_DELAY);
1984
1988 if (is_a0() || is_a2()) {
1985 if (is_a2(pdev)) {
1989 /* Enable TX equalization (0xe824) */
1990 writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
1991 udelay(AFE_REGISTER_WRITE_DELAY);
1992 }
1993
1994 /*
1995 * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
1996 * RDD=0x0(RX Detect Enabled) ....(0xe800) */
1997 writel(0x00004100, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
1998 udelay(AFE_REGISTER_WRITE_DELAY);
1999
2000 /* Leave DFE/FFE on */
1986 /* Enable TX equalization (0xe824) */
1987 writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
1988 udelay(AFE_REGISTER_WRITE_DELAY);
1989 }
1990
1991 /*
1992 * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
1993 * RDD=0x0(RX Detect Enabled) ....(0xe800) */
1994 writel(0x00004100, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
1995 udelay(AFE_REGISTER_WRITE_DELAY);
1996
1997 /* Leave DFE/FFE on */
2001 if (is_a0())
2002 writel(0x3F09983F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2003 else if (is_a2())
1998 if (is_a2(pdev))
2004 writel(0x3F11103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
1999 writel(0x3F11103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2005 else if (is_b0()) {
2000 else if (is_b0(pdev)) {
2006 writel(0x3F11103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2007 udelay(AFE_REGISTER_WRITE_DELAY);
2008 /* Enable TX equalization (0xe824) */
2009 writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2010 } else {
2011 writel(0x0140DF0F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1);
2012 udelay(AFE_REGISTER_WRITE_DELAY);
2013

--- 743 unchanged lines hidden --- 		2001 writel(0x3F11103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2002 udelay(AFE_REGISTER_WRITE_DELAY);
2003 /* Enable TX equalization (0xe824) */
2004 writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2005 } else {
2006 writel(0x0140DF0F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1);
2007 udelay(AFE_REGISTER_WRITE_DELAY);
2008

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