hpsa.c (2d8ad8719591fa803b0d589ed057fa46f49b7155) hpsa.c (9143a9612277abc6e4ddced2bc54a120734834c6)
1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *

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69MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
70MODULE_VERSION(HPSA_DRIVER_VERSION);
71MODULE_LICENSE("GPL");
72
73static int hpsa_allow_any;
74module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(hpsa_allow_any,
76 "Allow hpsa driver to access unknown HP Smart Array hardware");
1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *

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69MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
70MODULE_VERSION(HPSA_DRIVER_VERSION);
71MODULE_LICENSE("GPL");
72
73static int hpsa_allow_any;
74module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(hpsa_allow_any,
76 "Allow hpsa driver to access unknown HP Smart Array hardware");
77static int hpsa_simple_mode;
78module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(hpsa_simple_mode,
80 "Use 'simple mode' rather than 'performant mode'");
77
78/* define the PCI info for the cards we can control */
79static const struct pci_device_id hpsa_pci_device_id[] = {
80 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
81 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
82 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
83 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
84 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
85 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324a},
86 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324b},
87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
81
82/* define the PCI info for the cards we can control */
83static const struct pci_device_id hpsa_pci_device_id[] = {
84 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
85 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
86 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324a},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324b},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3250},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3251},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3252},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3253},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3254},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
93 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
94 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
95 {0,}
96};
97
98MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
99
100/* board_id = Subsystem Device ID & Vendor ID
101 * product = Marketing Name for the board
102 * access = Address of the struct of function pointers
103 */
104static struct board_type products[] = {
105 {0x3241103C, "Smart Array P212", &SA5_access},
106 {0x3243103C, "Smart Array P410", &SA5_access},
107 {0x3245103C, "Smart Array P410i", &SA5_access},
108 {0x3247103C, "Smart Array P411", &SA5_access},
109 {0x3249103C, "Smart Array P812", &SA5_access},
110 {0x324a103C, "Smart Array P712m", &SA5_access},
111 {0x324b103C, "Smart Array P711m", &SA5_access},
99 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
100 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
101 {0,}
102};
103
104MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
105
106/* board_id = Subsystem Device ID & Vendor ID
107 * product = Marketing Name for the board
108 * access = Address of the struct of function pointers
109 */
110static struct board_type products[] = {
111 {0x3241103C, "Smart Array P212", &SA5_access},
112 {0x3243103C, "Smart Array P410", &SA5_access},
113 {0x3245103C, "Smart Array P410i", &SA5_access},
114 {0x3247103C, "Smart Array P411", &SA5_access},
115 {0x3249103C, "Smart Array P812", &SA5_access},
116 {0x324a103C, "Smart Array P712m", &SA5_access},
117 {0x324b103C, "Smart Array P711m", &SA5_access},
112 {0x3250103C, "Smart Array", &SA5_access},
113 {0x3250113C, "Smart Array", &SA5_access},
114 {0x3250123C, "Smart Array", &SA5_access},
115 {0x3250133C, "Smart Array", &SA5_access},
116 {0x3250143C, "Smart Array", &SA5_access},
118 {0x3350103C, "Smart Array", &SA5_access},
119 {0x3351103C, "Smart Array", &SA5_access},
120 {0x3352103C, "Smart Array", &SA5_access},
121 {0x3353103C, "Smart Array", &SA5_access},
122 {0x3354103C, "Smart Array", &SA5_access},
123 {0x3355103C, "Smart Array", &SA5_access},
124 {0x3356103C, "Smart Array", &SA5_access},
117 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
118};
119
120static int number_of_controllers;
121
122static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
123static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
124static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);

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150static ssize_t raid_level_show(struct device *dev,
151 struct device_attribute *attr, char *buf);
152static ssize_t lunid_show(struct device *dev,
153 struct device_attribute *attr, char *buf);
154static ssize_t unique_id_show(struct device *dev,
155 struct device_attribute *attr, char *buf);
156static ssize_t host_show_firmware_revision(struct device *dev,
157 struct device_attribute *attr, char *buf);
125 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
126};
127
128static int number_of_controllers;
129
130static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
131static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
132static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);

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158static ssize_t raid_level_show(struct device *dev,
159 struct device_attribute *attr, char *buf);
160static ssize_t lunid_show(struct device *dev,
161 struct device_attribute *attr, char *buf);
162static ssize_t unique_id_show(struct device *dev,
163 struct device_attribute *attr, char *buf);
164static ssize_t host_show_firmware_revision(struct device *dev,
165 struct device_attribute *attr, char *buf);
166static ssize_t host_show_commands_outstanding(struct device *dev,
167 struct device_attribute *attr, char *buf);
168static ssize_t host_show_transport_mode(struct device *dev,
169 struct device_attribute *attr, char *buf);
158static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
159static ssize_t host_store_rescan(struct device *dev,
160 struct device_attribute *attr, const char *buf, size_t count);
161static int check_for_unit_attention(struct ctlr_info *h,
162 struct CommandList *c);
163static void check_ioctl_unit_attention(struct ctlr_info *h,
164 struct CommandList *c);
165/* performant mode helper functions */
166static void calc_bucket_map(int *bucket, int num_buckets,
167 int nsgs, int *bucket_map);
168static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
169static inline u32 next_command(struct ctlr_info *h);
170static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
171 void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
172 u64 *cfg_offset);
173static int __devinit hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
174 unsigned long *memory_bar);
175static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
170static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
171static ssize_t host_store_rescan(struct device *dev,
172 struct device_attribute *attr, const char *buf, size_t count);
173static int check_for_unit_attention(struct ctlr_info *h,
174 struct CommandList *c);
175static void check_ioctl_unit_attention(struct ctlr_info *h,
176 struct CommandList *c);
177/* performant mode helper functions */
178static void calc_bucket_map(int *bucket, int num_buckets,
179 int nsgs, int *bucket_map);
180static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
181static inline u32 next_command(struct ctlr_info *h);
182static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
183 void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
184 u64 *cfg_offset);
185static int __devinit hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
186 unsigned long *memory_bar);
187static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
188static int __devinit hpsa_wait_for_board_state(struct pci_dev *pdev,
189 void __iomem *vaddr, int wait_for_ready);
190#define BOARD_NOT_READY 0
191#define BOARD_READY 1
176
177static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
178static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
179static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
180static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
181static DEVICE_ATTR(firmware_revision, S_IRUGO,
182 host_show_firmware_revision, NULL);
192
193static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
194static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
195static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
196static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
197static DEVICE_ATTR(firmware_revision, S_IRUGO,
198 host_show_firmware_revision, NULL);
199static DEVICE_ATTR(commands_outstanding, S_IRUGO,
200 host_show_commands_outstanding, NULL);
201static DEVICE_ATTR(transport_mode, S_IRUGO,
202 host_show_transport_mode, NULL);
183
184static struct device_attribute *hpsa_sdev_attrs[] = {
185 &dev_attr_raid_level,
186 &dev_attr_lunid,
187 &dev_attr_unique_id,
188 NULL,
189};
190
191static struct device_attribute *hpsa_shost_attrs[] = {
192 &dev_attr_rescan,
193 &dev_attr_firmware_revision,
203
204static struct device_attribute *hpsa_sdev_attrs[] = {
205 &dev_attr_raid_level,
206 &dev_attr_lunid,
207 &dev_attr_unique_id,
208 NULL,
209};
210
211static struct device_attribute *hpsa_shost_attrs[] = {
212 &dev_attr_rescan,
213 &dev_attr_firmware_revision,
214 &dev_attr_commands_outstanding,
215 &dev_attr_transport_mode,
194 NULL,
195};
196
197static struct scsi_host_template hpsa_driver_template = {
198 .module = THIS_MODULE,
199 .name = "hpsa",
200 .proc_name = "hpsa",
201 .queuecommand = hpsa_scsi_queue_command,

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286 h = shost_to_hba(shost);
287 if (!h->hba_inquiry_data)
288 return 0;
289 fwrev = &h->hba_inquiry_data[32];
290 return snprintf(buf, 20, "%c%c%c%c\n",
291 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
292}
293
216 NULL,
217};
218
219static struct scsi_host_template hpsa_driver_template = {
220 .module = THIS_MODULE,
221 .name = "hpsa",
222 .proc_name = "hpsa",
223 .queuecommand = hpsa_scsi_queue_command,

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308 h = shost_to_hba(shost);
309 if (!h->hba_inquiry_data)
310 return 0;
311 fwrev = &h->hba_inquiry_data[32];
312 return snprintf(buf, 20, "%c%c%c%c\n",
313 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
314}
315
316static ssize_t host_show_commands_outstanding(struct device *dev,
317 struct device_attribute *attr, char *buf)
318{
319 struct Scsi_Host *shost = class_to_shost(dev);
320 struct ctlr_info *h = shost_to_hba(shost);
321
322 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
323}
324
325static ssize_t host_show_transport_mode(struct device *dev,
326 struct device_attribute *attr, char *buf)
327{
328 struct ctlr_info *h;
329 struct Scsi_Host *shost = class_to_shost(dev);
330
331 h = shost_to_hba(shost);
332 return snprintf(buf, 20, "%s\n",
333 h->transMethod & CFGTBL_Trans_Performant ?
334 "performant" : "simple");
335}
336
294/* Enqueuing and dequeuing functions for cmdlists. */
337/* Enqueuing and dequeuing functions for cmdlists. */
295static inline void addQ(struct hlist_head *list, struct CommandList *c)
338static inline void addQ(struct list_head *list, struct CommandList *c)
296{
339{
297 hlist_add_head(&c->list, list);
340 list_add_tail(&c->list, list);
298}
299
300static inline u32 next_command(struct ctlr_info *h)
301{
302 u32 a;
303
341}
342
343static inline u32 next_command(struct ctlr_info *h)
344{
345 u32 a;
346
304 if (unlikely(h->transMethod != CFGTBL_Trans_Performant))
347 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
305 return h->access.command_completed(h);
306
307 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
308 a = *(h->reply_pool_head); /* Next cmd in ring buffer */
309 (h->reply_pool_head)++;
310 h->commands_outstanding--;
311 } else {
312 a = FIFO_EMPTY;

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320}
321
322/* set_performant_mode: Modify the tag for cciss performant
323 * set bit 0 for pull model, bits 3-1 for block fetch
324 * register number
325 */
326static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
327{
348 return h->access.command_completed(h);
349
350 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
351 a = *(h->reply_pool_head); /* Next cmd in ring buffer */
352 (h->reply_pool_head)++;
353 h->commands_outstanding--;
354 } else {
355 a = FIFO_EMPTY;

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363}
364
365/* set_performant_mode: Modify the tag for cciss performant
366 * set bit 0 for pull model, bits 3-1 for block fetch
367 * register number
368 */
369static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
370{
328 if (likely(h->transMethod == CFGTBL_Trans_Performant))
371 if (likely(h->transMethod & CFGTBL_Trans_Performant))
329 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
330}
331
332static void enqueue_cmd_and_start_io(struct ctlr_info *h,
333 struct CommandList *c)
334{
335 unsigned long flags;
336
337 set_performant_mode(h, c);
338 spin_lock_irqsave(&h->lock, flags);
339 addQ(&h->reqQ, c);
340 h->Qdepth++;
341 start_io(h);
342 spin_unlock_irqrestore(&h->lock, flags);
343}
344
345static inline void removeQ(struct CommandList *c)
346{
372 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
373}
374
375static void enqueue_cmd_and_start_io(struct ctlr_info *h,
376 struct CommandList *c)
377{
378 unsigned long flags;
379
380 set_performant_mode(h, c);
381 spin_lock_irqsave(&h->lock, flags);
382 addQ(&h->reqQ, c);
383 h->Qdepth++;
384 start_io(h);
385 spin_unlock_irqrestore(&h->lock, flags);
386}
387
388static inline void removeQ(struct CommandList *c)
389{
347 if (WARN_ON(hlist_unhashed(&c->list)))
390 if (WARN_ON(list_empty(&c->list)))
348 return;
391 return;
349 hlist_del_init(&c->list);
392 list_del_init(&c->list);
350}
351
352static inline int is_hba_lunid(unsigned char scsi3addr[])
353{
354 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
355}
356
357static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])

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1125 cmd->result = DID_RESET << 16;
1126 dev_warn(&h->pdev->dev, "cp %p aborted do to an unsolicited "
1127 "abort\n", cp);
1128 break;
1129 case CMD_TIMEOUT:
1130 cmd->result = DID_TIME_OUT << 16;
1131 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1132 break;
393}
394
395static inline int is_hba_lunid(unsigned char scsi3addr[])
396{
397 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
398}
399
400static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])

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1168 cmd->result = DID_RESET << 16;
1169 dev_warn(&h->pdev->dev, "cp %p aborted do to an unsolicited "
1170 "abort\n", cp);
1171 break;
1172 case CMD_TIMEOUT:
1173 cmd->result = DID_TIME_OUT << 16;
1174 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1175 break;
1176 case CMD_UNABORTABLE:
1177 cmd->result = DID_ERROR << 16;
1178 dev_warn(&h->pdev->dev, "Command unabortable\n");
1179 break;
1133 default:
1134 cmd->result = DID_ERROR << 16;
1135 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1136 cp, ei->CommandStatus);
1137 }
1138 cmd->scsi_done(cmd);
1139 cmd_free(h, cp);
1140}

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1155 sh->max_cmd_len = MAX_COMMAND_SIZE;
1156 sh->max_lun = HPSA_MAX_LUN;
1157 sh->max_id = HPSA_MAX_LUN;
1158 sh->can_queue = h->nr_cmds;
1159 sh->cmd_per_lun = h->nr_cmds;
1160 sh->sg_tablesize = h->maxsgentries;
1161 h->scsi_host = sh;
1162 sh->hostdata[0] = (unsigned long) h;
1180 default:
1181 cmd->result = DID_ERROR << 16;
1182 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1183 cp, ei->CommandStatus);
1184 }
1185 cmd->scsi_done(cmd);
1186 cmd_free(h, cp);
1187}

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1202 sh->max_cmd_len = MAX_COMMAND_SIZE;
1203 sh->max_lun = HPSA_MAX_LUN;
1204 sh->max_id = HPSA_MAX_LUN;
1205 sh->can_queue = h->nr_cmds;
1206 sh->cmd_per_lun = h->nr_cmds;
1207 sh->sg_tablesize = h->maxsgentries;
1208 h->scsi_host = sh;
1209 sh->hostdata[0] = (unsigned long) h;
1163 sh->irq = h->intr[PERF_MODE_INT];
1210 sh->irq = h->intr[h->intr_mode];
1164 sh->unique_id = sh->irq;
1165 error = scsi_add_host(sh, &h->pdev->dev);
1166 if (error)
1167 goto fail_host_put;
1168 scsi_scan_host(sh);
1169 return 0;
1170
1171 fail_host_put:

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1290 dev_warn(d, "cp %p reports abort failed\n", cp);
1291 break;
1292 case CMD_UNSOLICITED_ABORT:
1293 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1294 break;
1295 case CMD_TIMEOUT:
1296 dev_warn(d, "cp %p timed out\n", cp);
1297 break;
1211 sh->unique_id = sh->irq;
1212 error = scsi_add_host(sh, &h->pdev->dev);
1213 if (error)
1214 goto fail_host_put;
1215 scsi_scan_host(sh);
1216 return 0;
1217
1218 fail_host_put:

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1337 dev_warn(d, "cp %p reports abort failed\n", cp);
1338 break;
1339 case CMD_UNSOLICITED_ABORT:
1340 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1341 break;
1342 case CMD_TIMEOUT:
1343 dev_warn(d, "cp %p timed out\n", cp);
1344 break;
1345 case CMD_UNABORTABLE:
1346 dev_warn(d, "Command unabortable\n");
1347 break;
1298 default:
1299 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1300 ei->CommandStatus);
1301 }
1302}
1303
1304static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1305 unsigned char page, unsigned char *buf,

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1590 return 0; /* It's the logical targets that may lack lun 0. */
1591
1592 if (!is_msa2xxx(h, tmpdevice))
1593 return 0; /* It's only the MSA2xxx that have this problem. */
1594
1595 if (lun == 0) /* if lun is 0, then obviously we have a lun 0. */
1596 return 0;
1597
1348 default:
1349 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1350 ei->CommandStatus);
1351 }
1352}
1353
1354static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1355 unsigned char page, unsigned char *buf,

--- 284 unchanged lines hidden (view full) ---

1640 return 0; /* It's the logical targets that may lack lun 0. */
1641
1642 if (!is_msa2xxx(h, tmpdevice))
1643 return 0; /* It's only the MSA2xxx that have this problem. */
1644
1645 if (lun == 0) /* if lun is 0, then obviously we have a lun 0. */
1646 return 0;
1647
1648 memset(scsi3addr, 0, 8);
1649 scsi3addr[3] = target;
1598 if (is_hba_lunid(scsi3addr))
1599 return 0; /* Don't add the RAID controller here. */
1600
1601 if (is_scsi_rev_5(h))
1602 return 0; /* p1210m doesn't need to do this. */
1603
1604#define MAX_MSA2XXX_ENCLOSURES 32
1605 if (*nmsa2xxx_enclosures >= MAX_MSA2XXX_ENCLOSURES) {
1606 dev_warn(&h->pdev->dev, "Maximum number of MSA2XXX "
1607 "enclosures exceeded. Check your hardware "
1608 "configuration.");
1609 return 0;
1610 }
1611
1650 if (is_hba_lunid(scsi3addr))
1651 return 0; /* Don't add the RAID controller here. */
1652
1653 if (is_scsi_rev_5(h))
1654 return 0; /* p1210m doesn't need to do this. */
1655
1656#define MAX_MSA2XXX_ENCLOSURES 32
1657 if (*nmsa2xxx_enclosures >= MAX_MSA2XXX_ENCLOSURES) {
1658 dev_warn(&h->pdev->dev, "Maximum number of MSA2XXX "
1659 "enclosures exceeded. Check your hardware "
1660 "configuration.");
1661 return 0;
1662 }
1663
1612 memset(scsi3addr, 0, 8);
1613 scsi3addr[3] = target;
1614 if (hpsa_update_device_info(h, scsi3addr, this_device))
1615 return 0;
1616 (*nmsa2xxx_enclosures)++;
1617 hpsa_set_bus_target_lun(this_device, bus, target, 0);
1618 set_bit(target, lunzerobits);
1619 return 1;
1620}
1621

--- 572 unchanged lines hidden (view full) ---

2194 c->err_info = h->errinfo_pool + i;
2195 memset(c->err_info, 0, sizeof(*c->err_info));
2196 err_dma_handle = h->errinfo_pool_dhandle
2197 + i * sizeof(*c->err_info);
2198 h->nr_allocs++;
2199
2200 c->cmdindex = i;
2201
1664 if (hpsa_update_device_info(h, scsi3addr, this_device))
1665 return 0;
1666 (*nmsa2xxx_enclosures)++;
1667 hpsa_set_bus_target_lun(this_device, bus, target, 0);
1668 set_bit(target, lunzerobits);
1669 return 1;
1670}
1671

--- 572 unchanged lines hidden (view full) ---

2244 c->err_info = h->errinfo_pool + i;
2245 memset(c->err_info, 0, sizeof(*c->err_info));
2246 err_dma_handle = h->errinfo_pool_dhandle
2247 + i * sizeof(*c->err_info);
2248 h->nr_allocs++;
2249
2250 c->cmdindex = i;
2251
2202 INIT_HLIST_NODE(&c->list);
2252 INIT_LIST_HEAD(&c->list);
2203 c->busaddr = (u32) cmd_dma_handle;
2204 temp64.val = (u64) err_dma_handle;
2205 c->ErrDesc.Addr.lower = temp64.val32.lower;
2206 c->ErrDesc.Addr.upper = temp64.val32.upper;
2207 c->ErrDesc.Len = sizeof(*c->err_info);
2208
2209 c->h = h;
2210 return c;

--- 21 unchanged lines hidden (view full) ---

2232
2233 if (c->err_info == NULL) {
2234 pci_free_consistent(h->pdev,
2235 sizeof(*c), c, cmd_dma_handle);
2236 return NULL;
2237 }
2238 memset(c->err_info, 0, sizeof(*c->err_info));
2239
2253 c->busaddr = (u32) cmd_dma_handle;
2254 temp64.val = (u64) err_dma_handle;
2255 c->ErrDesc.Addr.lower = temp64.val32.lower;
2256 c->ErrDesc.Addr.upper = temp64.val32.upper;
2257 c->ErrDesc.Len = sizeof(*c->err_info);
2258
2259 c->h = h;
2260 return c;

--- 21 unchanged lines hidden (view full) ---

2282
2283 if (c->err_info == NULL) {
2284 pci_free_consistent(h->pdev,
2285 sizeof(*c), c, cmd_dma_handle);
2286 return NULL;
2287 }
2288 memset(c->err_info, 0, sizeof(*c->err_info));
2289
2240 INIT_HLIST_NODE(&c->list);
2290 INIT_LIST_HEAD(&c->list);
2241 c->busaddr = (u32) cmd_dma_handle;
2242 temp64.val = (u64) err_dma_handle;
2243 c->ErrDesc.Addr.lower = temp64.val32.lower;
2244 c->ErrDesc.Addr.upper = temp64.val32.upper;
2245 c->ErrDesc.Len = sizeof(*c->err_info);
2246
2247 c->h = h;
2248 return c;

--- 13 unchanged lines hidden (view full) ---

2262{
2263 union u64bit temp64;
2264
2265 temp64.val32.lower = c->ErrDesc.Addr.lower;
2266 temp64.val32.upper = c->ErrDesc.Addr.upper;
2267 pci_free_consistent(h->pdev, sizeof(*c->err_info),
2268 c->err_info, (dma_addr_t) temp64.val);
2269 pci_free_consistent(h->pdev, sizeof(*c),
2291 c->busaddr = (u32) cmd_dma_handle;
2292 temp64.val = (u64) err_dma_handle;
2293 c->ErrDesc.Addr.lower = temp64.val32.lower;
2294 c->ErrDesc.Addr.upper = temp64.val32.upper;
2295 c->ErrDesc.Len = sizeof(*c->err_info);
2296
2297 c->h = h;
2298 return c;

--- 13 unchanged lines hidden (view full) ---

2312{
2313 union u64bit temp64;
2314
2315 temp64.val32.lower = c->ErrDesc.Addr.lower;
2316 temp64.val32.upper = c->ErrDesc.Addr.upper;
2317 pci_free_consistent(h->pdev, sizeof(*c->err_info),
2318 c->err_info, (dma_addr_t) temp64.val);
2319 pci_free_consistent(h->pdev, sizeof(*c),
2270 c, (dma_addr_t) c->busaddr);
2320 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
2271}
2272
2273#ifdef CONFIG_COMPAT
2274
2275static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
2276{
2277 IOCTL32_Command_struct __user *arg32 =
2278 (IOCTL32_Command_struct __user *) arg;
2279 IOCTL_Command_struct arg64;
2280 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
2281 int err;
2282 u32 cp;
2283
2321}
2322
2323#ifdef CONFIG_COMPAT
2324
2325static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
2326{
2327 IOCTL32_Command_struct __user *arg32 =
2328 (IOCTL32_Command_struct __user *) arg;
2329 IOCTL_Command_struct arg64;
2330 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
2331 int err;
2332 u32 cp;
2333
2334 memset(&arg64, 0, sizeof(arg64));
2284 err = 0;
2285 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
2286 sizeof(arg64.LUN_info));
2287 err |= copy_from_user(&arg64.Request, &arg32->Request,
2288 sizeof(arg64.Request));
2289 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
2290 sizeof(arg64.error_info));
2291 err |= get_user(arg64.buf_size, &arg32->buf_size);

--- 20 unchanged lines hidden (view full) ---

2312 BIG_IOCTL32_Command_struct __user *arg32 =
2313 (BIG_IOCTL32_Command_struct __user *) arg;
2314 BIG_IOCTL_Command_struct arg64;
2315 BIG_IOCTL_Command_struct __user *p =
2316 compat_alloc_user_space(sizeof(arg64));
2317 int err;
2318 u32 cp;
2319
2335 err = 0;
2336 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
2337 sizeof(arg64.LUN_info));
2338 err |= copy_from_user(&arg64.Request, &arg32->Request,
2339 sizeof(arg64.Request));
2340 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
2341 sizeof(arg64.error_info));
2342 err |= get_user(arg64.buf_size, &arg32->buf_size);

--- 20 unchanged lines hidden (view full) ---

2363 BIG_IOCTL32_Command_struct __user *arg32 =
2364 (BIG_IOCTL32_Command_struct __user *) arg;
2365 BIG_IOCTL_Command_struct arg64;
2366 BIG_IOCTL_Command_struct __user *p =
2367 compat_alloc_user_space(sizeof(arg64));
2368 int err;
2369 u32 cp;
2370
2371 memset(&arg64, 0, sizeof(arg64));
2320 err = 0;
2321 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
2322 sizeof(arg64.LUN_info));
2323 err |= copy_from_user(&arg64.Request, &arg32->Request,
2324 sizeof(arg64.Request));
2325 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
2326 sizeof(arg64.error_info));
2327 err |= get_user(arg64.buf_size, &arg32->buf_size);

--- 100 unchanged lines hidden (view full) ---

2428 if ((iocommand.buf_size < 1) &&
2429 (iocommand.Request.Type.Direction != XFER_NONE)) {
2430 return -EINVAL;
2431 }
2432 if (iocommand.buf_size > 0) {
2433 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
2434 if (buff == NULL)
2435 return -EFAULT;
2372 err = 0;
2373 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
2374 sizeof(arg64.LUN_info));
2375 err |= copy_from_user(&arg64.Request, &arg32->Request,
2376 sizeof(arg64.Request));
2377 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
2378 sizeof(arg64.error_info));
2379 err |= get_user(arg64.buf_size, &arg32->buf_size);

--- 100 unchanged lines hidden (view full) ---

2480 if ((iocommand.buf_size < 1) &&
2481 (iocommand.Request.Type.Direction != XFER_NONE)) {
2482 return -EINVAL;
2483 }
2484 if (iocommand.buf_size > 0) {
2485 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
2486 if (buff == NULL)
2487 return -EFAULT;
2436 }
2437 if (iocommand.Request.Type.Direction == XFER_WRITE) {
2438 /* Copy the data into the buffer we created */
2439 if (copy_from_user(buff, iocommand.buf, iocommand.buf_size)) {
2440 kfree(buff);
2441 return -EFAULT;
2488 if (iocommand.Request.Type.Direction == XFER_WRITE) {
2489 /* Copy the data into the buffer we created */
2490 if (copy_from_user(buff, iocommand.buf,
2491 iocommand.buf_size)) {
2492 kfree(buff);
2493 return -EFAULT;
2494 }
2495 } else {
2496 memset(buff, 0, iocommand.buf_size);
2442 }
2497 }
2443 } else
2444 memset(buff, 0, iocommand.buf_size);
2498 }
2445 c = cmd_special_alloc(h);
2446 if (c == NULL) {
2447 kfree(buff);
2448 return -ENOMEM;
2449 }
2450 /* Fill in the command type */
2451 c->cmd_type = CMD_IOCTL_PEND;
2452 /* Fill in Command Header */

--- 29 unchanged lines hidden (view full) ---

2482 /* Copy the error information out */
2483 memcpy(&iocommand.error_info, c->err_info,
2484 sizeof(iocommand.error_info));
2485 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
2486 kfree(buff);
2487 cmd_special_free(h, c);
2488 return -EFAULT;
2489 }
2499 c = cmd_special_alloc(h);
2500 if (c == NULL) {
2501 kfree(buff);
2502 return -ENOMEM;
2503 }
2504 /* Fill in the command type */
2505 c->cmd_type = CMD_IOCTL_PEND;
2506 /* Fill in Command Header */

--- 29 unchanged lines hidden (view full) ---

2536 /* Copy the error information out */
2537 memcpy(&iocommand.error_info, c->err_info,
2538 sizeof(iocommand.error_info));
2539 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
2540 kfree(buff);
2541 cmd_special_free(h, c);
2542 return -EFAULT;
2543 }
2490
2491 if (iocommand.Request.Type.Direction == XFER_READ) {
2544 if (iocommand.Request.Type.Direction == XFER_READ &&
2545 iocommand.buf_size > 0) {
2492 /* Copy the data out of the buffer we created */
2493 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
2494 kfree(buff);
2495 cmd_special_free(h, c);
2496 return -EFAULT;
2497 }
2498 }
2499 kfree(buff);

--- 76 unchanged lines hidden (view full) ---

2576 }
2577 c = cmd_special_alloc(h);
2578 if (c == NULL) {
2579 status = -ENOMEM;
2580 goto cleanup1;
2581 }
2582 c->cmd_type = CMD_IOCTL_PEND;
2583 c->Header.ReplyQueue = 0;
2546 /* Copy the data out of the buffer we created */
2547 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
2548 kfree(buff);
2549 cmd_special_free(h, c);
2550 return -EFAULT;
2551 }
2552 }
2553 kfree(buff);

--- 76 unchanged lines hidden (view full) ---

2630 }
2631 c = cmd_special_alloc(h);
2632 if (c == NULL) {
2633 status = -ENOMEM;
2634 goto cleanup1;
2635 }
2636 c->cmd_type = CMD_IOCTL_PEND;
2637 c->Header.ReplyQueue = 0;
2584
2585 if (ioc->buf_size > 0) {
2586 c->Header.SGList = sg_used;
2587 c->Header.SGTotal = sg_used;
2588 } else {
2589 c->Header.SGList = 0;
2590 c->Header.SGTotal = 0;
2591 }
2638 c->Header.SGList = c->Header.SGTotal = sg_used;
2592 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
2593 c->Header.Tag.lower = c->busaddr;
2594 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
2595 if (ioc->buf_size > 0) {
2596 int i;
2597 for (i = 0; i < sg_used; i++) {
2598 temp64.val = pci_map_single(h->pdev, buff[i],
2599 buff_size[i], PCI_DMA_BIDIRECTIONAL);
2600 c->SG[i].Addr.lower = temp64.val32.lower;
2601 c->SG[i].Addr.upper = temp64.val32.upper;
2602 c->SG[i].Len = buff_size[i];
2603 /* we are not chaining */
2604 c->SG[i].Ext = 0;
2605 }
2606 }
2607 hpsa_scsi_do_simple_cmd_core(h, c);
2639 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
2640 c->Header.Tag.lower = c->busaddr;
2641 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
2642 if (ioc->buf_size > 0) {
2643 int i;
2644 for (i = 0; i < sg_used; i++) {
2645 temp64.val = pci_map_single(h->pdev, buff[i],
2646 buff_size[i], PCI_DMA_BIDIRECTIONAL);
2647 c->SG[i].Addr.lower = temp64.val32.lower;
2648 c->SG[i].Addr.upper = temp64.val32.upper;
2649 c->SG[i].Len = buff_size[i];
2650 /* we are not chaining */
2651 c->SG[i].Ext = 0;
2652 }
2653 }
2654 hpsa_scsi_do_simple_cmd_core(h, c);
2608 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
2655 if (sg_used)
2656 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
2609 check_ioctl_unit_attention(h, c);
2610 /* Copy the error information out */
2611 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
2612 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
2613 cmd_special_free(h, c);
2614 status = -EFAULT;
2615 goto cleanup1;
2616 }
2657 check_ioctl_unit_attention(h, c);
2658 /* Copy the error information out */
2659 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
2660 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
2661 cmd_special_free(h, c);
2662 status = -EFAULT;
2663 goto cleanup1;
2664 }
2617 if (ioc->Request.Type.Direction == XFER_READ) {
2665 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
2618 /* Copy the data out of the buffer we created */
2619 BYTE __user *ptr = ioc->buf;
2620 for (i = 0; i < sg_used; i++) {
2621 if (copy_to_user(ptr, buff[i], buff_size[i])) {
2622 cmd_special_free(h, c);
2623 status = -EFAULT;
2624 goto cleanup1;
2625 }

--- 179 unchanged lines hidden (view full) ---

2805
2806/* Takes cmds off the submission queue and sends them to the hardware,
2807 * then puts them on the queue of cmds waiting for completion.
2808 */
2809static void start_io(struct ctlr_info *h)
2810{
2811 struct CommandList *c;
2812
2666 /* Copy the data out of the buffer we created */
2667 BYTE __user *ptr = ioc->buf;
2668 for (i = 0; i < sg_used; i++) {
2669 if (copy_to_user(ptr, buff[i], buff_size[i])) {
2670 cmd_special_free(h, c);
2671 status = -EFAULT;
2672 goto cleanup1;
2673 }

--- 179 unchanged lines hidden (view full) ---

2853
2854/* Takes cmds off the submission queue and sends them to the hardware,
2855 * then puts them on the queue of cmds waiting for completion.
2856 */
2857static void start_io(struct ctlr_info *h)
2858{
2859 struct CommandList *c;
2860
2813 while (!hlist_empty(&h->reqQ)) {
2814 c = hlist_entry(h->reqQ.first, struct CommandList, list);
2861 while (!list_empty(&h->reqQ)) {
2862 c = list_entry(h->reqQ.next, struct CommandList, list);
2815 /* can't do anything if fifo is full */
2816 if ((h->access.fifo_full(h))) {
2817 dev_warn(&h->pdev->dev, "fifo full\n");
2818 break;
2819 }
2820
2821 /* Get the first entry from the Request Q */
2822 removeQ(c);

--- 39 unchanged lines hidden (view full) ---

2862 if (likely(c->cmd_type == CMD_SCSI))
2863 complete_scsi_command(c, 0, raw_tag);
2864 else if (c->cmd_type == CMD_IOCTL_PEND)
2865 complete(c->waiting);
2866}
2867
2868static inline u32 hpsa_tag_contains_index(u32 tag)
2869{
2863 /* can't do anything if fifo is full */
2864 if ((h->access.fifo_full(h))) {
2865 dev_warn(&h->pdev->dev, "fifo full\n");
2866 break;
2867 }
2868
2869 /* Get the first entry from the Request Q */
2870 removeQ(c);

--- 39 unchanged lines hidden (view full) ---

2910 if (likely(c->cmd_type == CMD_SCSI))
2911 complete_scsi_command(c, 0, raw_tag);
2912 else if (c->cmd_type == CMD_IOCTL_PEND)
2913 complete(c->waiting);
2914}
2915
2916static inline u32 hpsa_tag_contains_index(u32 tag)
2917{
2870#define DIRECT_LOOKUP_BIT 0x10
2871 return tag & DIRECT_LOOKUP_BIT;
2872}
2873
2874static inline u32 hpsa_tag_to_index(u32 tag)
2875{
2918 return tag & DIRECT_LOOKUP_BIT;
2919}
2920
2921static inline u32 hpsa_tag_to_index(u32 tag)
2922{
2876#define DIRECT_LOOKUP_SHIFT 5
2877 return tag >> DIRECT_LOOKUP_SHIFT;
2878}
2879
2923 return tag >> DIRECT_LOOKUP_SHIFT;
2924}
2925
2880static inline u32 hpsa_tag_discard_error_bits(u32 tag)
2926
2927static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
2881{
2928{
2882#define HPSA_ERROR_BITS 0x03
2883 return tag & ~HPSA_ERROR_BITS;
2929#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
2930#define HPSA_SIMPLE_ERROR_BITS 0x03
2931 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
2932 return tag & ~HPSA_SIMPLE_ERROR_BITS;
2933 return tag & ~HPSA_PERF_ERROR_BITS;
2884}
2885
2886/* process completion of an indexed ("direct lookup") command */
2887static inline u32 process_indexed_cmd(struct ctlr_info *h,
2888 u32 raw_tag)
2889{
2890 u32 tag_index;
2891 struct CommandList *c;

--- 7 unchanged lines hidden (view full) ---

2899}
2900
2901/* process completion of a non-indexed command */
2902static inline u32 process_nonindexed_cmd(struct ctlr_info *h,
2903 u32 raw_tag)
2904{
2905 u32 tag;
2906 struct CommandList *c = NULL;
2934}
2935
2936/* process completion of an indexed ("direct lookup") command */
2937static inline u32 process_indexed_cmd(struct ctlr_info *h,
2938 u32 raw_tag)
2939{
2940 u32 tag_index;
2941 struct CommandList *c;

--- 7 unchanged lines hidden (view full) ---

2949}
2950
2951/* process completion of a non-indexed command */
2952static inline u32 process_nonindexed_cmd(struct ctlr_info *h,
2953 u32 raw_tag)
2954{
2955 u32 tag;
2956 struct CommandList *c = NULL;
2907 struct hlist_node *tmp;
2908
2957
2909 tag = hpsa_tag_discard_error_bits(raw_tag);
2910 hlist_for_each_entry(c, tmp, &h->cmpQ, list) {
2958 tag = hpsa_tag_discard_error_bits(h, raw_tag);
2959 list_for_each_entry(c, &h->cmpQ, list) {
2911 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
2912 finish_cmd(c, raw_tag);
2913 return next_command(h);
2914 }
2915 }
2916 bad_tag(h, h->nr_cmds + 1, raw_tag);
2917 return next_command(h);
2918}

--- 33 unchanged lines hidden (view full) ---

2952 raw_tag = process_indexed_cmd(h, raw_tag);
2953 else
2954 raw_tag = process_nonindexed_cmd(h, raw_tag);
2955 }
2956 spin_unlock_irqrestore(&h->lock, flags);
2957 return IRQ_HANDLED;
2958}
2959
2960 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
2961 finish_cmd(c, raw_tag);
2962 return next_command(h);
2963 }
2964 }
2965 bad_tag(h, h->nr_cmds + 1, raw_tag);
2966 return next_command(h);
2967}

--- 33 unchanged lines hidden (view full) ---

3001 raw_tag = process_indexed_cmd(h, raw_tag);
3002 else
3003 raw_tag = process_nonindexed_cmd(h, raw_tag);
3004 }
3005 spin_unlock_irqrestore(&h->lock, flags);
3006 return IRQ_HANDLED;
3007}
3008
2960/* Send a message CDB to the firmware. */
3009/* Send a message CDB to the firmware. Careful, this only works
3010 * in simple mode, not performant mode due to the tag lookup.
3011 * We only ever use this immediately after a controller reset.
3012 */
2961static __devinit int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
2962 unsigned char type)
2963{
2964 struct Command {
2965 struct CommandListHeader CommandHeader;
2966 struct RequestBlock Request;
2967 struct ErrDescriptor ErrorDescriptor;
2968 };

--- 49 unchanged lines hidden (view full) ---

3018 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
3019 cmd->ErrorDescriptor.Addr.upper = 0;
3020 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
3021
3022 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
3023
3024 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
3025 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
3013static __devinit int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
3014 unsigned char type)
3015{
3016 struct Command {
3017 struct CommandListHeader CommandHeader;
3018 struct RequestBlock Request;
3019 struct ErrDescriptor ErrorDescriptor;
3020 };

--- 49 unchanged lines hidden (view full) ---

3070 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
3071 cmd->ErrorDescriptor.Addr.upper = 0;
3072 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
3073
3074 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
3075
3076 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
3077 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
3026 if (hpsa_tag_discard_error_bits(tag) == paddr32)
3078 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
3027 break;
3028 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
3029 }
3030
3031 iounmap(vaddr);
3032
3033 /* we leak the DMA buffer here ... no choice since the controller could
3034 * still complete the command.

--- 15 unchanged lines hidden (view full) ---

3050 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
3051 opcode, type);
3052 return 0;
3053}
3054
3055#define hpsa_soft_reset_controller(p) hpsa_message(p, 1, 0)
3056#define hpsa_noop(p) hpsa_message(p, 3, 0)
3057
3079 break;
3080 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
3081 }
3082
3083 iounmap(vaddr);
3084
3085 /* we leak the DMA buffer here ... no choice since the controller could
3086 * still complete the command.

--- 15 unchanged lines hidden (view full) ---

3102 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
3103 opcode, type);
3104 return 0;
3105}
3106
3107#define hpsa_soft_reset_controller(p) hpsa_message(p, 1, 0)
3108#define hpsa_noop(p) hpsa_message(p, 3, 0)
3109
3058static __devinit int hpsa_reset_msi(struct pci_dev *pdev)
3059{
3060/* the #defines are stolen from drivers/pci/msi.h. */
3061#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
3062#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
3063
3064 int pos;
3065 u16 control = 0;
3066
3067 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
3068 if (pos) {
3069 pci_read_config_word(pdev, msi_control_reg(pos), &control);
3070 if (control & PCI_MSI_FLAGS_ENABLE) {
3071 dev_info(&pdev->dev, "resetting MSI\n");
3072 pci_write_config_word(pdev, msi_control_reg(pos),
3073 control & ~PCI_MSI_FLAGS_ENABLE);
3074 }
3075 }
3076
3077 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3078 if (pos) {
3079 pci_read_config_word(pdev, msi_control_reg(pos), &control);
3080 if (control & PCI_MSIX_FLAGS_ENABLE) {
3081 dev_info(&pdev->dev, "resetting MSI-X\n");
3082 pci_write_config_word(pdev, msi_control_reg(pos),
3083 control & ~PCI_MSIX_FLAGS_ENABLE);
3084 }
3085 }
3086
3087 return 0;
3088}
3089
3090static int hpsa_controller_hard_reset(struct pci_dev *pdev,
3091 void * __iomem vaddr, bool use_doorbell)
3092{
3093 u16 pmcsr;
3094 int pos;
3095
3096 if (use_doorbell) {
3097 /* For everything after the P600, the PCI power state method

--- 39 unchanged lines hidden (view full) ---

3137 return 0;
3138}
3139
3140/* This does a hard reset of the controller using PCI power management
3141 * states or the using the doorbell register.
3142 */
3143static __devinit int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
3144{
3110static int hpsa_controller_hard_reset(struct pci_dev *pdev,
3111 void * __iomem vaddr, bool use_doorbell)
3112{
3113 u16 pmcsr;
3114 int pos;
3115
3116 if (use_doorbell) {
3117 /* For everything after the P600, the PCI power state method

--- 39 unchanged lines hidden (view full) ---

3157 return 0;
3158}
3159
3160/* This does a hard reset of the controller using PCI power management
3161 * states or the using the doorbell register.
3162 */
3163static __devinit int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
3164{
3145 u16 saved_config_space[32];
3146 u64 cfg_offset;
3147 u32 cfg_base_addr;
3148 u64 cfg_base_addr_index;
3149 void __iomem *vaddr;
3150 unsigned long paddr;
3151 u32 misc_fw_support, active_transport;
3165 u64 cfg_offset;
3166 u32 cfg_base_addr;
3167 u64 cfg_base_addr_index;
3168 void __iomem *vaddr;
3169 unsigned long paddr;
3170 u32 misc_fw_support, active_transport;
3152 int rc, i;
3171 int rc;
3153 struct CfgTable __iomem *cfgtable;
3154 bool use_doorbell;
3155 u32 board_id;
3172 struct CfgTable __iomem *cfgtable;
3173 bool use_doorbell;
3174 u32 board_id;
3175 u16 command_register;
3156
3157 /* For controllers as old as the P600, this is very nearly
3158 * the same thing as
3159 *
3160 * pci_save_state(pci_dev);
3161 * pci_set_power_state(pci_dev, PCI_D3hot);
3162 * pci_set_power_state(pci_dev, PCI_D0);
3163 * pci_restore_state(pci_dev);
3164 *
3176
3177 /* For controllers as old as the P600, this is very nearly
3178 * the same thing as
3179 *
3180 * pci_save_state(pci_dev);
3181 * pci_set_power_state(pci_dev, PCI_D3hot);
3182 * pci_set_power_state(pci_dev, PCI_D0);
3183 * pci_restore_state(pci_dev);
3184 *
3165 * but we can't use these nice canned kernel routines on
3166 * kexec, because they also check the MSI/MSI-X state in PCI
3167 * configuration space and do the wrong thing when it is
3168 * set/cleared. Also, the pci_save/restore_state functions
3169 * violate the ordering requirements for restoring the
3170 * configuration space from the CCISS document (see the
3171 * comment below). So we roll our own ....
3172 *
3173 * For controllers newer than the P600, the pci power state
3174 * method of resetting doesn't work so we have another way
3175 * using the doorbell register.
3176 */
3177
3178 /* Exclude 640x boards. These are two pci devices in one slot
3179 * which share a battery backed cache module. One controls the
3180 * cache, the other accesses the cache through the one that controls
3181 * it. If we reset the one controlling the cache, the other will
3182 * likely not be happy. Just forbid resetting this conjoined mess.
3183 * The 640x isn't really supported by hpsa anyway.
3184 */
3185 * For controllers newer than the P600, the pci power state
3186 * method of resetting doesn't work so we have another way
3187 * using the doorbell register.
3188 */
3189
3190 /* Exclude 640x boards. These are two pci devices in one slot
3191 * which share a battery backed cache module. One controls the
3192 * cache, the other accesses the cache through the one that controls
3193 * it. If we reset the one controlling the cache, the other will
3194 * likely not be happy. Just forbid resetting this conjoined mess.
3195 * The 640x isn't really supported by hpsa anyway.
3196 */
3185 hpsa_lookup_board_id(pdev, &board_id);
3197 rc = hpsa_lookup_board_id(pdev, &board_id);
3198 if (rc < 0) {
3199 dev_warn(&pdev->dev, "Not resetting device.\n");
3200 return -ENODEV;
3201 }
3186 if (board_id == 0x409C0E11 || board_id == 0x409D0E11)
3187 return -ENOTSUPP;
3188
3202 if (board_id == 0x409C0E11 || board_id == 0x409D0E11)
3203 return -ENOTSUPP;
3204
3189 for (i = 0; i < 32; i++)
3190 pci_read_config_word(pdev, 2*i, &saved_config_space[i]);
3205 /* Save the PCI command register */
3206 pci_read_config_word(pdev, 4, &command_register);
3207 /* Turn the board off. This is so that later pci_restore_state()
3208 * won't turn the board on before the rest of config space is ready.
3209 */
3210 pci_disable_device(pdev);
3211 pci_save_state(pdev);
3191
3212
3192
3193 /* find the first memory BAR, so we can find the cfg table */
3194 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
3195 if (rc)
3196 return rc;
3197 vaddr = remap_pci_mem(paddr, 0x250);
3198 if (!vaddr)
3199 return -ENOMEM;
3200

--- 8 unchanged lines hidden (view full) ---

3209 rc = -ENOMEM;
3210 goto unmap_vaddr;
3211 }
3212
3213 /* If reset via doorbell register is supported, use that. */
3214 misc_fw_support = readl(&cfgtable->misc_fw_support);
3215 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
3216
3213 /* find the first memory BAR, so we can find the cfg table */
3214 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
3215 if (rc)
3216 return rc;
3217 vaddr = remap_pci_mem(paddr, 0x250);
3218 if (!vaddr)
3219 return -ENOMEM;
3220

--- 8 unchanged lines hidden (view full) ---

3229 rc = -ENOMEM;
3230 goto unmap_vaddr;
3231 }
3232
3233 /* If reset via doorbell register is supported, use that. */
3234 misc_fw_support = readl(&cfgtable->misc_fw_support);
3235 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
3236
3217 /* The doorbell reset seems to cause lockups on some Smart
3218 * Arrays (e.g. P410, P410i, maybe others). Until this is
3219 * fixed or at least isolated, avoid the doorbell reset.
3220 */
3221 use_doorbell = 0;
3222
3223 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
3224 if (rc)
3225 goto unmap_cfgtable;
3226
3237 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
3238 if (rc)
3239 goto unmap_cfgtable;
3240
3227 /* Restore the PCI configuration space. The Open CISS
3228 * Specification says, "Restore the PCI Configuration
3229 * Registers, offsets 00h through 60h. It is important to
3230 * restore the command register, 16-bits at offset 04h,
3231 * last. Do not restore the configuration status register,
3232 * 16-bits at offset 06h." Note that the offset is 2*i.
3233 */
3234 for (i = 0; i < 32; i++) {
3235 if (i == 2 || i == 3)
3236 continue;
3237 pci_write_config_word(pdev, 2*i, saved_config_space[i]);
3241 pci_restore_state(pdev);
3242 rc = pci_enable_device(pdev);
3243 if (rc) {
3244 dev_warn(&pdev->dev, "failed to enable device.\n");
3245 goto unmap_cfgtable;
3238 }
3246 }
3239 wmb();
3240 pci_write_config_word(pdev, 4, saved_config_space[2]);
3247 pci_write_config_word(pdev, 4, command_register);
3241
3242 /* Some devices (notably the HP Smart Array 5i Controller)
3243 need a little pause here */
3244 msleep(HPSA_POST_RESET_PAUSE_MSECS);
3245
3248
3249 /* Some devices (notably the HP Smart Array 5i Controller)
3250 need a little pause here */
3251 msleep(HPSA_POST_RESET_PAUSE_MSECS);
3252
3253 /* Wait for board to become not ready, then ready. */
3254 dev_info(&pdev->dev, "Waiting for board to become ready.\n");
3255 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
3256 if (rc)
3257 dev_warn(&pdev->dev,
3258 "failed waiting for board to become not ready\n");
3259 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
3260 if (rc) {
3261 dev_warn(&pdev->dev,
3262 "failed waiting for board to become ready\n");
3263 goto unmap_cfgtable;
3264 }
3265 dev_info(&pdev->dev, "board ready.\n");
3266
3246 /* Controller should be in simple mode at this point. If it's not,
3247 * It means we're on one of those controllers which doesn't support
3248 * the doorbell reset method and on which the PCI power management reset
3249 * method doesn't work (P800, for example.)
3267 /* Controller should be in simple mode at this point. If it's not,
3268 * It means we're on one of those controllers which doesn't support
3269 * the doorbell reset method and on which the PCI power management reset
3270 * method doesn't work (P800, for example.)
3250 * In those cases, pretend the reset worked and hope for the best.
3271 * In those cases, don't try to proceed, as it generally doesn't work.
3251 */
3252 active_transport = readl(&cfgtable->TransportActive);
3253 if (active_transport & PERFORMANT_MODE) {
3254 dev_warn(&pdev->dev, "Unable to successfully reset controller,"
3272 */
3273 active_transport = readl(&cfgtable->TransportActive);
3274 if (active_transport & PERFORMANT_MODE) {
3275 dev_warn(&pdev->dev, "Unable to successfully reset controller,"
3255 " proceeding anyway.\n");
3256 rc = -ENOTSUPP;
3276 " Ignoring controller.\n");
3277 rc = -ENODEV;
3257 }
3258
3259unmap_cfgtable:
3260 iounmap(cfgtable);
3261
3262unmap_vaddr:
3263 iounmap(vaddr);
3264 return rc;

--- 116 unchanged lines hidden (view full) ---

3381 if (!pci_enable_msi(h->pdev))
3382 h->msi_vector = 1;
3383 else
3384 dev_warn(&h->pdev->dev, "MSI init failed\n");
3385 }
3386default_int_mode:
3387#endif /* CONFIG_PCI_MSI */
3388 /* if we get here we're going to use the default interrupt mode */
3278 }
3279
3280unmap_cfgtable:
3281 iounmap(cfgtable);
3282
3283unmap_vaddr:
3284 iounmap(vaddr);
3285 return rc;

--- 116 unchanged lines hidden (view full) ---

3402 if (!pci_enable_msi(h->pdev))
3403 h->msi_vector = 1;
3404 else
3405 dev_warn(&h->pdev->dev, "MSI init failed\n");
3406 }
3407default_int_mode:
3408#endif /* CONFIG_PCI_MSI */
3409 /* if we get here we're going to use the default interrupt mode */
3389 h->intr[PERF_MODE_INT] = h->pdev->irq;
3410 h->intr[h->intr_mode] = h->pdev->irq;
3390}
3391
3392static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
3393{
3394 int i;
3395 u32 subsystem_vendor_id, subsystem_device_id;
3396
3397 subsystem_vendor_id = pdev->subsystem_vendor;

--- 35 unchanged lines hidden (view full) ---

3433 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3434 *memory_bar);
3435 return 0;
3436 }
3437 dev_warn(&pdev->dev, "no memory BAR found\n");
3438 return -ENODEV;
3439}
3440
3411}
3412
3413static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
3414{
3415 int i;
3416 u32 subsystem_vendor_id, subsystem_device_id;
3417
3418 subsystem_vendor_id = pdev->subsystem_vendor;

--- 35 unchanged lines hidden (view full) ---

3454 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3455 *memory_bar);
3456 return 0;
3457 }
3458 dev_warn(&pdev->dev, "no memory BAR found\n");
3459 return -ENODEV;
3460}
3461
3441static int __devinit hpsa_wait_for_board_ready(struct ctlr_info *h)
3462static int __devinit hpsa_wait_for_board_state(struct pci_dev *pdev,
3463 void __iomem *vaddr, int wait_for_ready)
3442{
3464{
3443 int i;
3465 int i, iterations;
3444 u32 scratchpad;
3466 u32 scratchpad;
3467 if (wait_for_ready)
3468 iterations = HPSA_BOARD_READY_ITERATIONS;
3469 else
3470 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
3445
3471
3446 for (i = 0; i < HPSA_BOARD_READY_ITERATIONS; i++) {
3447 scratchpad = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
3448 if (scratchpad == HPSA_FIRMWARE_READY)
3449 return 0;
3472 for (i = 0; i < iterations; i++) {
3473 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
3474 if (wait_for_ready) {
3475 if (scratchpad == HPSA_FIRMWARE_READY)
3476 return 0;
3477 } else {
3478 if (scratchpad != HPSA_FIRMWARE_READY)
3479 return 0;
3480 }
3450 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
3451 }
3481 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
3482 }
3452 dev_warn(&h->pdev->dev, "board not ready, timed out.\n");
3483 dev_warn(&pdev->dev, "board not ready, timed out.\n");
3453 return -ENODEV;
3454}
3455
3456static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
3457 void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
3458 u64 *cfg_offset)
3459{
3460 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);

--- 31 unchanged lines hidden (view full) ---

3492 if (!h->transtable)
3493 return -ENOMEM;
3494 return 0;
3495}
3496
3497static void __devinit hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
3498{
3499 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
3484 return -ENODEV;
3485}
3486
3487static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
3488 void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
3489 u64 *cfg_offset)
3490{
3491 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);

--- 31 unchanged lines hidden (view full) ---

3523 if (!h->transtable)
3524 return -ENOMEM;
3525 return 0;
3526}
3527
3528static void __devinit hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
3529{
3530 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
3531
3532 /* Limit commands in memory limited kdump scenario. */
3533 if (reset_devices && h->max_commands > 32)
3534 h->max_commands = 32;
3535
3500 if (h->max_commands < 16) {
3501 dev_warn(&h->pdev->dev, "Controller reports "
3502 "max supported commands of %d, an obvious lie. "
3503 "Using 16. Ensure that firmware is up to date.\n",
3504 h->max_commands);
3505 h->max_commands = 16;
3506 }
3507}

--- 58 unchanged lines hidden (view full) ---

3566 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
3567 dma_prefetch |= 0x8000;
3568 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
3569}
3570
3571static void __devinit hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
3572{
3573 int i;
3536 if (h->max_commands < 16) {
3537 dev_warn(&h->pdev->dev, "Controller reports "
3538 "max supported commands of %d, an obvious lie. "
3539 "Using 16. Ensure that firmware is up to date.\n",
3540 h->max_commands);
3541 h->max_commands = 16;
3542 }
3543}

--- 58 unchanged lines hidden (view full) ---

3602 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
3603 dma_prefetch |= 0x8000;
3604 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
3605}
3606
3607static void __devinit hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
3608{
3609 int i;
3610 u32 doorbell_value;
3611 unsigned long flags;
3574
3575 /* under certain very rare conditions, this can take awhile.
3576 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
3577 * as we enter this code.)
3578 */
3579 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
3612
3613 /* under certain very rare conditions, this can take awhile.
3614 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
3615 * as we enter this code.)
3616 */
3617 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
3580 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
3618 spin_lock_irqsave(&h->lock, flags);
3619 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
3620 spin_unlock_irqrestore(&h->lock, flags);
3621 if (!(doorbell_value & CFGTBL_ChangeReq))
3581 break;
3582 /* delay and try again */
3622 break;
3623 /* delay and try again */
3583 msleep(10);
3624 usleep_range(10000, 20000);
3584 }
3585}
3586
3587static int __devinit hpsa_enter_simple_mode(struct ctlr_info *h)
3588{
3589 u32 trans_support;
3590
3591 trans_support = readl(&(h->cfgtable->TransportSupport));

--- 6 unchanged lines hidden (view full) ---

3598 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3599 hpsa_wait_for_mode_change_ack(h);
3600 print_cfg_table(&h->pdev->dev, h->cfgtable);
3601 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
3602 dev_warn(&h->pdev->dev,
3603 "unable to get board into simple mode\n");
3604 return -ENODEV;
3605 }
3625 }
3626}
3627
3628static int __devinit hpsa_enter_simple_mode(struct ctlr_info *h)
3629{
3630 u32 trans_support;
3631
3632 trans_support = readl(&(h->cfgtable->TransportSupport));

--- 6 unchanged lines hidden (view full) ---

3639 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3640 hpsa_wait_for_mode_change_ack(h);
3641 print_cfg_table(&h->pdev->dev, h->cfgtable);
3642 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
3643 dev_warn(&h->pdev->dev,
3644 "unable to get board into simple mode\n");
3645 return -ENODEV;
3646 }
3647 h->transMethod = CFGTBL_Trans_Simple;
3606 return 0;
3607}
3608
3609static int __devinit hpsa_pci_init(struct ctlr_info *h)
3610{
3611 int prod_index, err;
3612
3613 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);

--- 22 unchanged lines hidden (view full) ---

3636 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3637 if (err)
3638 goto err_out_free_res;
3639 h->vaddr = remap_pci_mem(h->paddr, 0x250);
3640 if (!h->vaddr) {
3641 err = -ENOMEM;
3642 goto err_out_free_res;
3643 }
3648 return 0;
3649}
3650
3651static int __devinit hpsa_pci_init(struct ctlr_info *h)
3652{
3653 int prod_index, err;
3654
3655 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);

--- 22 unchanged lines hidden (view full) ---

3678 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3679 if (err)
3680 goto err_out_free_res;
3681 h->vaddr = remap_pci_mem(h->paddr, 0x250);
3682 if (!h->vaddr) {
3683 err = -ENOMEM;
3684 goto err_out_free_res;
3685 }
3644 err = hpsa_wait_for_board_ready(h);
3686 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
3645 if (err)
3646 goto err_out_free_res;
3647 err = hpsa_find_cfgtables(h);
3648 if (err)
3649 goto err_out_free_res;
3650 hpsa_find_board_params(h);
3651
3652 if (!hpsa_CISS_signature_present(h)) {

--- 52 unchanged lines hidden (view full) ---

3705 * but it's already (and still) up and running in
3706 * "performant mode". Or, it might be 640x, which can't reset
3707 * due to concerns about shared bbwc between 6402/6404 pair.
3708 */
3709 if (rc == -ENOTSUPP)
3710 return 0; /* just try to do the kdump anyhow. */
3711 if (rc)
3712 return -ENODEV;
3687 if (err)
3688 goto err_out_free_res;
3689 err = hpsa_find_cfgtables(h);
3690 if (err)
3691 goto err_out_free_res;
3692 hpsa_find_board_params(h);
3693
3694 if (!hpsa_CISS_signature_present(h)) {

--- 52 unchanged lines hidden (view full) ---

3747 * but it's already (and still) up and running in
3748 * "performant mode". Or, it might be 640x, which can't reset
3749 * due to concerns about shared bbwc between 6402/6404 pair.
3750 */
3751 if (rc == -ENOTSUPP)
3752 return 0; /* just try to do the kdump anyhow. */
3753 if (rc)
3754 return -ENODEV;
3713 if (hpsa_reset_msi(pdev))
3714 return -ENODEV;
3715
3716 /* Now try to get the controller to respond to a no-op */
3717 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
3718 if (hpsa_noop(pdev) == 0)
3719 break;
3720 else
3721 dev_warn(&pdev->dev, "no-op failed%s\n",
3722 (i < 11 ? "; re-trying" : ""));

--- 21 unchanged lines hidden (view full) ---

3744#define COMMANDLIST_ALIGNMENT 32
3745 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
3746 h = kzalloc(sizeof(*h), GFP_KERNEL);
3747 if (!h)
3748 return -ENOMEM;
3749
3750 h->pdev = pdev;
3751 h->busy_initializing = 1;
3755
3756 /* Now try to get the controller to respond to a no-op */
3757 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
3758 if (hpsa_noop(pdev) == 0)
3759 break;
3760 else
3761 dev_warn(&pdev->dev, "no-op failed%s\n",
3762 (i < 11 ? "; re-trying" : ""));

--- 21 unchanged lines hidden (view full) ---

3784#define COMMANDLIST_ALIGNMENT 32
3785 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
3786 h = kzalloc(sizeof(*h), GFP_KERNEL);
3787 if (!h)
3788 return -ENOMEM;
3789
3790 h->pdev = pdev;
3791 h->busy_initializing = 1;
3752 INIT_HLIST_HEAD(&h->cmpQ);
3753 INIT_HLIST_HEAD(&h->reqQ);
3792 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
3793 INIT_LIST_HEAD(&h->cmpQ);
3794 INIT_LIST_HEAD(&h->reqQ);
3795 spin_lock_init(&h->lock);
3796 spin_lock_init(&h->scan_lock);
3754 rc = hpsa_pci_init(h);
3755 if (rc != 0)
3756 goto clean1;
3757
3758 sprintf(h->devname, "hpsa%d", number_of_controllers);
3759 h->ctlr = number_of_controllers;
3760 number_of_controllers++;
3761

--- 10 unchanged lines hidden (view full) ---

3772 goto clean1;
3773 }
3774 }
3775
3776 /* make sure the board interrupts are off */
3777 h->access.set_intr_mask(h, HPSA_INTR_OFF);
3778
3779 if (h->msix_vector || h->msi_vector)
3797 rc = hpsa_pci_init(h);
3798 if (rc != 0)
3799 goto clean1;
3800
3801 sprintf(h->devname, "hpsa%d", number_of_controllers);
3802 h->ctlr = number_of_controllers;
3803 number_of_controllers++;
3804

--- 10 unchanged lines hidden (view full) ---

3815 goto clean1;
3816 }
3817 }
3818
3819 /* make sure the board interrupts are off */
3820 h->access.set_intr_mask(h, HPSA_INTR_OFF);
3821
3822 if (h->msix_vector || h->msi_vector)
3780 rc = request_irq(h->intr[PERF_MODE_INT], do_hpsa_intr_msi,
3823 rc = request_irq(h->intr[h->intr_mode], do_hpsa_intr_msi,
3781 IRQF_DISABLED, h->devname, h);
3782 else
3824 IRQF_DISABLED, h->devname, h);
3825 else
3783 rc = request_irq(h->intr[PERF_MODE_INT], do_hpsa_intr_intx,
3826 rc = request_irq(h->intr[h->intr_mode], do_hpsa_intr_intx,
3784 IRQF_DISABLED, h->devname, h);
3785 if (rc) {
3786 dev_err(&pdev->dev, "unable to get irq %d for %s\n",
3827 IRQF_DISABLED, h->devname, h);
3828 if (rc) {
3829 dev_err(&pdev->dev, "unable to get irq %d for %s\n",
3787 h->intr[PERF_MODE_INT], h->devname);
3830 h->intr[h->intr_mode], h->devname);
3788 goto clean2;
3789 }
3790
3791 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
3792 h->devname, pdev->device,
3831 goto clean2;
3832 }
3833
3834 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
3835 h->devname, pdev->device,
3793 h->intr[PERF_MODE_INT], dac ? "" : " not");
3836 h->intr[h->intr_mode], dac ? "" : " not");
3794
3795 h->cmd_pool_bits =
3796 kmalloc(((h->nr_cmds + BITS_PER_LONG -
3797 1) / BITS_PER_LONG) * sizeof(unsigned long), GFP_KERNEL);
3798 h->cmd_pool = pci_alloc_consistent(h->pdev,
3799 h->nr_cmds * sizeof(*h->cmd_pool),
3800 &(h->cmd_pool_dhandle));
3801 h->errinfo_pool = pci_alloc_consistent(h->pdev,
3802 h->nr_cmds * sizeof(*h->errinfo_pool),
3803 &(h->errinfo_pool_dhandle));
3804 if ((h->cmd_pool_bits == NULL)
3805 || (h->cmd_pool == NULL)
3806 || (h->errinfo_pool == NULL)) {
3807 dev_err(&pdev->dev, "out of memory");
3808 rc = -ENOMEM;
3809 goto clean4;
3810 }
3811 if (hpsa_allocate_sg_chain_blocks(h))
3812 goto clean4;
3837
3838 h->cmd_pool_bits =
3839 kmalloc(((h->nr_cmds + BITS_PER_LONG -
3840 1) / BITS_PER_LONG) * sizeof(unsigned long), GFP_KERNEL);
3841 h->cmd_pool = pci_alloc_consistent(h->pdev,
3842 h->nr_cmds * sizeof(*h->cmd_pool),
3843 &(h->cmd_pool_dhandle));
3844 h->errinfo_pool = pci_alloc_consistent(h->pdev,
3845 h->nr_cmds * sizeof(*h->errinfo_pool),
3846 &(h->errinfo_pool_dhandle));
3847 if ((h->cmd_pool_bits == NULL)
3848 || (h->cmd_pool == NULL)
3849 || (h->errinfo_pool == NULL)) {
3850 dev_err(&pdev->dev, "out of memory");
3851 rc = -ENOMEM;
3852 goto clean4;
3853 }
3854 if (hpsa_allocate_sg_chain_blocks(h))
3855 goto clean4;
3813 spin_lock_init(&h->lock);
3814 spin_lock_init(&h->scan_lock);
3815 init_waitqueue_head(&h->scan_wait_queue);
3816 h->scan_finished = 1; /* no scan currently in progress */
3817
3818 pci_set_drvdata(pdev, h);
3819 memset(h->cmd_pool_bits, 0,
3820 ((h->nr_cmds + BITS_PER_LONG -
3821 1) / BITS_PER_LONG) * sizeof(unsigned long));
3822

--- 15 unchanged lines hidden (view full) ---

3838 pci_free_consistent(h->pdev,
3839 h->nr_cmds * sizeof(struct CommandList),
3840 h->cmd_pool, h->cmd_pool_dhandle);
3841 if (h->errinfo_pool)
3842 pci_free_consistent(h->pdev,
3843 h->nr_cmds * sizeof(struct ErrorInfo),
3844 h->errinfo_pool,
3845 h->errinfo_pool_dhandle);
3856 init_waitqueue_head(&h->scan_wait_queue);
3857 h->scan_finished = 1; /* no scan currently in progress */
3858
3859 pci_set_drvdata(pdev, h);
3860 memset(h->cmd_pool_bits, 0,
3861 ((h->nr_cmds + BITS_PER_LONG -
3862 1) / BITS_PER_LONG) * sizeof(unsigned long));
3863

--- 15 unchanged lines hidden (view full) ---

3879 pci_free_consistent(h->pdev,
3880 h->nr_cmds * sizeof(struct CommandList),
3881 h->cmd_pool, h->cmd_pool_dhandle);
3882 if (h->errinfo_pool)
3883 pci_free_consistent(h->pdev,
3884 h->nr_cmds * sizeof(struct ErrorInfo),
3885 h->errinfo_pool,
3886 h->errinfo_pool_dhandle);
3846 free_irq(h->intr[PERF_MODE_INT], h);
3887 free_irq(h->intr[h->intr_mode], h);
3847clean2:
3848clean1:
3849 h->busy_initializing = 0;
3850 kfree(h);
3851 return rc;
3852}
3853
3854static void hpsa_flush_cache(struct ctlr_info *h)

--- 27 unchanged lines hidden (view full) ---

3882
3883 h = pci_get_drvdata(pdev);
3884 /* Turn board interrupts off and send the flush cache command
3885 * sendcmd will turn off interrupt, and send the flush...
3886 * To write all data in the battery backed cache to disks
3887 */
3888 hpsa_flush_cache(h);
3889 h->access.set_intr_mask(h, HPSA_INTR_OFF);
3888clean2:
3889clean1:
3890 h->busy_initializing = 0;
3891 kfree(h);
3892 return rc;
3893}
3894
3895static void hpsa_flush_cache(struct ctlr_info *h)

--- 27 unchanged lines hidden (view full) ---

3923
3924 h = pci_get_drvdata(pdev);
3925 /* Turn board interrupts off and send the flush cache command
3926 * sendcmd will turn off interrupt, and send the flush...
3927 * To write all data in the battery backed cache to disks
3928 */
3929 hpsa_flush_cache(h);
3930 h->access.set_intr_mask(h, HPSA_INTR_OFF);
3890 free_irq(h->intr[PERF_MODE_INT], h);
3931 free_irq(h->intr[h->intr_mode], h);
3891#ifdef CONFIG_PCI_MSI
3892 if (h->msix_vector)
3893 pci_disable_msix(h->pdev);
3894 else if (h->msi_vector)
3895 pci_disable_msi(h->pdev);
3896#endif /* CONFIG_PCI_MSI */
3897}
3898

--- 85 unchanged lines hidden (view full) ---

3984 break;
3985 }
3986 }
3987 /* for a command with i SG entries, use bucket b. */
3988 bucket_map[i] = b;
3989 }
3990}
3991
3932#ifdef CONFIG_PCI_MSI
3933 if (h->msix_vector)
3934 pci_disable_msix(h->pdev);
3935 else if (h->msi_vector)
3936 pci_disable_msi(h->pdev);
3937#endif /* CONFIG_PCI_MSI */
3938}
3939

--- 85 unchanged lines hidden (view full) ---

4025 break;
4026 }
4027 }
4028 /* for a command with i SG entries, use bucket b. */
4029 bucket_map[i] = b;
4030 }
4031}
4032
3992static __devinit void hpsa_enter_performant_mode(struct ctlr_info *h)
4033static __devinit void hpsa_enter_performant_mode(struct ctlr_info *h,
4034 u32 use_short_tags)
3993{
3994 int i;
3995 unsigned long register_value;
3996
3997 /* This is a bit complicated. There are 8 registers on
3998 * the controller which we write to to tell it 8 different
3999 * sizes of commands which there may be. It's a way of
4000 * reducing the DMA done to fetch each command. Encoded into

--- 31 unchanged lines hidden (view full) ---

4032
4033 /* size of controller ring buffer */
4034 writel(h->max_commands, &h->transtable->RepQSize);
4035 writel(1, &h->transtable->RepQCount);
4036 writel(0, &h->transtable->RepQCtrAddrLow32);
4037 writel(0, &h->transtable->RepQCtrAddrHigh32);
4038 writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
4039 writel(0, &h->transtable->RepQAddr0High32);
4035{
4036 int i;
4037 unsigned long register_value;
4038
4039 /* This is a bit complicated. There are 8 registers on
4040 * the controller which we write to to tell it 8 different
4041 * sizes of commands which there may be. It's a way of
4042 * reducing the DMA done to fetch each command. Encoded into

--- 31 unchanged lines hidden (view full) ---

4074
4075 /* size of controller ring buffer */
4076 writel(h->max_commands, &h->transtable->RepQSize);
4077 writel(1, &h->transtable->RepQCount);
4078 writel(0, &h->transtable->RepQCtrAddrLow32);
4079 writel(0, &h->transtable->RepQCtrAddrHigh32);
4080 writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
4081 writel(0, &h->transtable->RepQAddr0High32);
4040 writel(CFGTBL_Trans_Performant,
4082 writel(CFGTBL_Trans_Performant | use_short_tags,
4041 &(h->cfgtable->HostWrite.TransportRequest));
4042 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
4043 hpsa_wait_for_mode_change_ack(h);
4044 register_value = readl(&(h->cfgtable->TransportActive));
4045 if (!(register_value & CFGTBL_Trans_Performant)) {
4046 dev_warn(&h->pdev->dev, "unable to get board into"
4047 " performant mode\n");
4048 return;
4049 }
4083 &(h->cfgtable->HostWrite.TransportRequest));
4084 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
4085 hpsa_wait_for_mode_change_ack(h);
4086 register_value = readl(&(h->cfgtable->TransportActive));
4087 if (!(register_value & CFGTBL_Trans_Performant)) {
4088 dev_warn(&h->pdev->dev, "unable to get board into"
4089 " performant mode\n");
4090 return;
4091 }
4092 /* Change the access methods to the performant access methods */
4093 h->access = SA5_performant_access;
4094 h->transMethod = CFGTBL_Trans_Performant;
4050}
4051
4052static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
4053{
4054 u32 trans_support;
4055
4095}
4096
4097static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
4098{
4099 u32 trans_support;
4100
4101 if (hpsa_simple_mode)
4102 return;
4103
4056 trans_support = readl(&(h->cfgtable->TransportSupport));
4057 if (!(trans_support & PERFORMANT_MODE))
4058 return;
4059
4060 hpsa_get_max_perf_mode_cmds(h);
4061 h->max_sg_entries = 32;
4062 /* Performant mode ring buffer and supporting data structures */
4063 h->reply_pool_size = h->max_commands * sizeof(u64);
4064 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
4065 &(h->reply_pool_dhandle));
4066
4067 /* Need a block fetch table for performant mode */
4068 h->blockFetchTable = kmalloc(((h->max_sg_entries+1) *
4069 sizeof(u32)), GFP_KERNEL);
4070
4071 if ((h->reply_pool == NULL)
4072 || (h->blockFetchTable == NULL))
4073 goto clean_up;
4074
4104 trans_support = readl(&(h->cfgtable->TransportSupport));
4105 if (!(trans_support & PERFORMANT_MODE))
4106 return;
4107
4108 hpsa_get_max_perf_mode_cmds(h);
4109 h->max_sg_entries = 32;
4110 /* Performant mode ring buffer and supporting data structures */
4111 h->reply_pool_size = h->max_commands * sizeof(u64);
4112 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
4113 &(h->reply_pool_dhandle));
4114
4115 /* Need a block fetch table for performant mode */
4116 h->blockFetchTable = kmalloc(((h->max_sg_entries+1) *
4117 sizeof(u32)), GFP_KERNEL);
4118
4119 if ((h->reply_pool == NULL)
4120 || (h->blockFetchTable == NULL))
4121 goto clean_up;
4122
4075 hpsa_enter_performant_mode(h);
4123 hpsa_enter_performant_mode(h,
4124 trans_support & CFGTBL_Trans_use_short_tags);
4076
4125
4077 /* Change the access methods to the performant access methods */
4078 h->access = SA5_performant_access;
4079 h->transMethod = CFGTBL_Trans_Performant;
4080
4081 return;
4082
4083clean_up:
4084 if (h->reply_pool)
4085 pci_free_consistent(h->pdev, h->reply_pool_size,
4086 h->reply_pool, h->reply_pool_dhandle);
4087 kfree(h->blockFetchTable);
4088}

--- 17 unchanged lines hidden --- 		4126 return;
4127
4128clean_up:
4129 if (h->reply_pool)
4130 pci_free_consistent(h->pdev, h->reply_pool_size,
4131 h->reply_pool, h->reply_pool_dhandle);
4132 kfree(h->blockFetchTable);
4133}

--- 17 unchanged lines hidden ---