rtc-pcf2127.c (fc16599e0153e91ba12d856e40f6fc56906077f1) rtc-pcf2127.c (420cc9e850dbc8e6ea7dd1e53d62d64cd8766354)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An I2C and SPI driver for the NXP PCF2127/29 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions

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54#define PCF2127_BIT_CLKOUT_OTPR BIT(5)
55/* Watchdog registers */
56#define PCF2127_REG_WD_CTL 0x10
57#define PCF2127_BIT_WD_CTL_TF0 BIT(0)
58#define PCF2127_BIT_WD_CTL_TF1 BIT(1)
59#define PCF2127_BIT_WD_CTL_CD0 BIT(6)
60#define PCF2127_BIT_WD_CTL_CD1 BIT(7)
61#define PCF2127_REG_WD_VAL 0x11
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An I2C and SPI driver for the NXP PCF2127/29 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions

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54#define PCF2127_BIT_CLKOUT_OTPR BIT(5)
55/* Watchdog registers */
56#define PCF2127_REG_WD_CTL 0x10
57#define PCF2127_BIT_WD_CTL_TF0 BIT(0)
58#define PCF2127_BIT_WD_CTL_TF1 BIT(1)
59#define PCF2127_BIT_WD_CTL_CD0 BIT(6)
60#define PCF2127_BIT_WD_CTL_CD1 BIT(7)
61#define PCF2127_REG_WD_VAL 0x11
62/* Tamper timestamp registers */
63#define PCF2127_REG_TS_CTRL 0x12
62/* Tamper timestamp1 registers */
63#define PCF2127_REG_TS1_BASE 0x12
64#define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
65#define PCF2127_BIT_TS_CTRL_TSM BIT(7)
66/*
67 * RAM registers
68 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
69 * battery backed and can survive a power outage.
70 * PCF2129 doesn't have this feature.
71 */

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81
82/* Mask for currently enabled interrupts */
83#define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
84#define PCF2127_CTRL2_IRQ_MASK ( \
85 PCF2127_BIT_CTRL2_AF | \
86 PCF2127_BIT_CTRL2_WDTF | \
87 PCF2127_BIT_CTRL2_TSF2)
88
64#define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
65#define PCF2127_BIT_TS_CTRL_TSM BIT(7)
66/*
67 * RAM registers
68 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
69 * battery backed and can survive a power outage.
70 * PCF2129 doesn't have this feature.
71 */

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81
82/* Mask for currently enabled interrupts */
83#define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
84#define PCF2127_CTRL2_IRQ_MASK ( \
85 PCF2127_BIT_CTRL2_AF | \
86 PCF2127_BIT_CTRL2_WDTF | \
87 PCF2127_BIT_CTRL2_TSF2)
88
89#define PCF2127_MAX_TS_SUPPORTED 1
90
89enum pcf21xx_type {
90 PCF2127,
91 PCF2129,
92 PCF21XX_LAST_ID
93};
94
91enum pcf21xx_type {
92 PCF2127,
93 PCF2129,
94 PCF21XX_LAST_ID
95};
96
97struct pcf21xx_ts_config {
98 u8 reg_base; /* Base register to read timestamp values. */
99
100 /*
101 * If the TS input pin is driven to GND, an interrupt can be generated
102 * (supported by all variants).
103 */
104 u8 gnd_detect_reg; /* Interrupt control register address. */
105 u8 gnd_detect_bit; /* Interrupt bit. */
106
107 /*
108 * If the TS input pin is driven to an intermediate level between GND
109 * and supply, an interrupt can be generated (optional feature depending
110 * on variant).
111 */
112 u8 inter_detect_reg; /* Interrupt control register address. */
113 u8 inter_detect_bit; /* Interrupt bit. */
114
115 u8 ie_reg; /* Interrupt enable control register. */
116 u8 ie_bit; /* Interrupt enable bit. */
117};
118
95struct pcf21xx_config {
96 int type; /* IC variant */
97 int max_register;
98 unsigned int has_nvmem:1;
99 unsigned int has_bit_wd_ctl_cd0:1;
100 u8 reg_time_base; /* Time/date base register. */
101 u8 regs_alarm_base; /* Alarm function base registers. */
102 u8 reg_wd_ctl; /* Watchdog control register. */
103 u8 reg_wd_val; /* Watchdog value register. */
104 u8 reg_clkout; /* Clkout register. */
119struct pcf21xx_config {
120 int type; /* IC variant */
121 int max_register;
122 unsigned int has_nvmem:1;
123 unsigned int has_bit_wd_ctl_cd0:1;
124 u8 reg_time_base; /* Time/date base register. */
125 u8 regs_alarm_base; /* Alarm function base registers. */
126 u8 reg_wd_ctl; /* Watchdog control register. */
127 u8 reg_wd_val; /* Watchdog value register. */
128 u8 reg_clkout; /* Clkout register. */
129 unsigned int ts_count;
130 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED];
131 struct attribute_group attribute_group;
105};
106
107struct pcf2127 {
108 struct rtc_device *rtc;
109 struct watchdog_device wdd;
110 struct regmap *regmap;
111 const struct pcf21xx_config *cfg;
132};
133
134struct pcf2127 {
135 struct rtc_device *rtc;
136 struct watchdog_device wdd;
137 struct regmap *regmap;
138 const struct pcf21xx_config *cfg;
112 time64_t ts;
113 bool ts_valid;
114 bool irq_enabled;
139 bool irq_enabled;
140 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */
141 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */
115};
116
117/*
118 * In the routines that deal directly with the pcf2127 hardware, we use
119 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
120 */
121static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
122{

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436 buf, sizeof(buf));
437 if (ret)
438 return ret;
439
440 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
441}
442
443/*
142};
143
144/*
145 * In the routines that deal directly with the pcf2127 hardware, we use
146 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
147 */
148static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
149{

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463 buf, sizeof(buf));
464 if (ret)
465 return ret;
466
467 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
468}
469
470/*
444 * This function reads ctrl2 register, caller is responsible for calling
445 * pcf2127_wdt_active_ping()
471 * This function reads one timestamp function data, caller is responsible for
472 * calling pcf2127_wdt_active_ping()
446 */
473 */
447static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts)
474static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts,
475 int ts_id)
448{
449 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
450 struct rtc_time tm;
451 int ret;
452 unsigned char data[7];
453
476{
477 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
478 struct rtc_time tm;
479 int ret;
480 unsigned char data[7];
481
454 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_TS_CTRL, data,
455 sizeof(data));
482 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base,
483 data, sizeof(data));
456 if (ret) {
457 dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
458 return ret;
459 }
460
461 dev_dbg(dev,
462 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
463 __func__, data[1], data[2], data[3], data[4], data[5], data[6]);

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477 dev_err(dev, "Invalid timestamp. ret=%d\n", ret);
478 return ret;
479 }
480
481 *ts = rtc_tm_to_time64(&tm);
482 return 0;
483};
484
484 if (ret) {
485 dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
486 return ret;
487 }
488
489 dev_dbg(dev,
490 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
491 __func__, data[1], data[2], data[3], data[4], data[5], data[6]);

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505 dev_err(dev, "Invalid timestamp. ret=%d\n", ret);
506 return ret;
507 }
508
509 *ts = rtc_tm_to_time64(&tm);
510 return 0;
511};
512
485static void pcf2127_rtc_ts_snapshot(struct device *dev)
513static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id)
486{
487 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
488 int ret;
489
514{
515 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
516 int ret;
517
518 if (ts_id >= pcf2127->cfg->ts_count)
519 return;
520
490 /* Let userspace read the first timestamp */
521 /* Let userspace read the first timestamp */
491 if (pcf2127->ts_valid)
522 if (pcf2127->ts_valid[ts_id])
492 return;
493
523 return;
524
494 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts);
525 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id);
495 if (!ret)
526 if (!ret)
496 pcf2127->ts_valid = true;
527 pcf2127->ts_valid[ts_id] = true;
497}
498
499static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
500{
501 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
502 unsigned int ctrl1, ctrl2;
503 int ret = 0;
504

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509 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
510 if (ret)
511 return IRQ_NONE;
512
513 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
514 return IRQ_NONE;
515
516 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
528}
529
530static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
531{
532 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
533 unsigned int ctrl1, ctrl2;
534 int ret = 0;
535

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540 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
541 if (ret)
542 return IRQ_NONE;
543
544 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
545 return IRQ_NONE;
546
547 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
517 pcf2127_rtc_ts_snapshot(dev);
548 pcf2127_rtc_ts_snapshot(dev, 0);
518
519 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
520 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
521 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
522
523 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
524 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
525 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);

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538 .set_time = pcf2127_rtc_set_time,
539 .read_alarm = pcf2127_rtc_read_alarm,
540 .set_alarm = pcf2127_rtc_set_alarm,
541 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
542};
543
544/* sysfs interface */
545
549
550 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
551 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
552 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
553
554 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
555 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
556 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);

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569 .set_time = pcf2127_rtc_set_time,
570 .read_alarm = pcf2127_rtc_read_alarm,
571 .set_alarm = pcf2127_rtc_set_alarm,
572 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
573};
574
575/* sysfs interface */
576
546static ssize_t timestamp0_store(struct device *dev,
547 struct device_attribute *attr,
548 const char *buf, size_t count)
577static ssize_t timestamp_store(struct device *dev,
578 struct device_attribute *attr,
579 const char *buf, size_t count, int ts_id)
549{
550 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
551 int ret;
552
580{
581 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
582 int ret;
583
584 if (ts_id >= pcf2127->cfg->ts_count)
585 return 0;
586
553 if (pcf2127->irq_enabled) {
587 if (pcf2127->irq_enabled) {
554 pcf2127->ts_valid = false;
588 pcf2127->ts_valid[ts_id] = false;
555 } else {
589 } else {
556 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
557 PCF2127_BIT_CTRL1_TSF1, 0);
590 /* Always clear GND interrupt bit. */
591 ret = regmap_update_bits(pcf2127->regmap,
592 pcf2127->cfg->ts[ts_id].gnd_detect_reg,
593 pcf2127->cfg->ts[ts_id].gnd_detect_bit,
594 0);
595
558 if (ret) {
596 if (ret) {
559 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret);
597 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret);
560 return ret;
561 }
562
598 return ret;
599 }
600
563 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
564 PCF2127_BIT_CTRL2_TSF2, 0);
565 if (ret) {
566 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret);
567 return ret;
601 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
602 /* Clear intermediate level interrupt bit if supported. */
603 ret = regmap_update_bits(pcf2127->regmap,
604 pcf2127->cfg->ts[ts_id].inter_detect_reg,
605 pcf2127->cfg->ts[ts_id].inter_detect_bit,
606 0);
607 if (ret) {
608 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n",
609 __func__, ret);
610 return ret;
611 }
568 }
569
570 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
571 if (ret)
572 return ret;
573 }
574
575 return count;
612 }
613
614 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
615 if (ret)
616 return ret;
617 }
618
619 return count;
620}
621
622static ssize_t timestamp0_store(struct device *dev,
623 struct device_attribute *attr,
624 const char *buf, size_t count)
625{
626 return timestamp_store(dev, attr, buf, count, 0);
576};
577
627};
628
578static ssize_t timestamp0_show(struct device *dev,
579 struct device_attribute *attr, char *buf)
629static ssize_t timestamp_show(struct device *dev,
630 struct device_attribute *attr, char *buf,
631 int ts_id)
580{
581 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
632{
633 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
582 unsigned int ctrl1, ctrl2;
583 int ret;
584 time64_t ts;
585
634 int ret;
635 time64_t ts;
636
637 if (ts_id >= pcf2127->cfg->ts_count)
638 return 0;
639
586 if (pcf2127->irq_enabled) {
640 if (pcf2127->irq_enabled) {
587 if (!pcf2127->ts_valid)
641 if (!pcf2127->ts_valid[ts_id])
588 return 0;
642 return 0;
589 ts = pcf2127->ts;
643 ts = pcf2127->ts[ts_id];
590 } else {
644 } else {
591 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
592 if (ret)
593 return 0;
645 u8 valid_low = 0;
646 u8 valid_inter = 0;
647 unsigned int ctrl;
594
648
595 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
649 /* Check if TS input pin is driven to GND, supported by all
650 * variants.
651 */
652 ret = regmap_read(pcf2127->regmap,
653 pcf2127->cfg->ts[ts_id].gnd_detect_reg,
654 &ctrl);
596 if (ret)
597 return 0;
598
655 if (ret)
656 return 0;
657
599 if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) &&
600 !(ctrl2 & PCF2127_BIT_CTRL2_TSF2))
658 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit;
659
660 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
661 /* Check if TS input pin is driven to intermediate level
662 * between GND and supply, if supported by variant.
663 */
664 ret = regmap_read(pcf2127->regmap,
665 pcf2127->cfg->ts[ts_id].inter_detect_reg,
666 &ctrl);
667 if (ret)
668 return 0;
669
670 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit;
671 }
672
673 if (!valid_low && !valid_inter)
601 return 0;
602
674 return 0;
675
603 ret = pcf2127_rtc_ts_read(dev->parent, &ts);
676 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id);
604 if (ret)
605 return 0;
606
607 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
608 if (ret)
609 return ret;
610 }
611 return sprintf(buf, "%llu\n", (unsigned long long)ts);
677 if (ret)
678 return 0;
679
680 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
681 if (ret)
682 return ret;
683 }
684 return sprintf(buf, "%llu\n", (unsigned long long)ts);
685}
686
687static ssize_t timestamp0_show(struct device *dev,
688 struct device_attribute *attr, char *buf)
689{
690 return timestamp_show(dev, attr, buf, 0);
612};
613
614static DEVICE_ATTR_RW(timestamp0);
615
616static struct attribute *pcf2127_attrs[] = {
617 &dev_attr_timestamp0.attr,
618 NULL
619};
620
691};
692
693static DEVICE_ATTR_RW(timestamp0);
694
695static struct attribute *pcf2127_attrs[] = {
696 &dev_attr_timestamp0.attr,
697 NULL
698};
699
621static const struct attribute_group pcf2127_attr_group = {
622 .attrs = pcf2127_attrs,
623};
624
625static struct pcf21xx_config pcf21xx_cfg[] = {
626 [PCF2127] = {
627 .type = PCF2127,
628 .max_register = 0x1d,
629 .has_nvmem = 1,
630 .has_bit_wd_ctl_cd0 = 1,
631 .reg_time_base = PCF2127_REG_TIME_BASE,
632 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
633 .reg_wd_ctl = PCF2127_REG_WD_CTL,
634 .reg_wd_val = PCF2127_REG_WD_VAL,
635 .reg_clkout = PCF2127_REG_CLKOUT,
700static struct pcf21xx_config pcf21xx_cfg[] = {
701 [PCF2127] = {
702 .type = PCF2127,
703 .max_register = 0x1d,
704 .has_nvmem = 1,
705 .has_bit_wd_ctl_cd0 = 1,
706 .reg_time_base = PCF2127_REG_TIME_BASE,
707 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
708 .reg_wd_ctl = PCF2127_REG_WD_CTL,
709 .reg_wd_val = PCF2127_REG_WD_VAL,
710 .reg_clkout = PCF2127_REG_CLKOUT,
711 .ts_count = 1,
712 .ts[0] = {
713 .reg_base = PCF2127_REG_TS1_BASE,
714 .gnd_detect_reg = PCF2127_REG_CTRL1,
715 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
716 .inter_detect_reg = PCF2127_REG_CTRL2,
717 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
718 .ie_reg = PCF2127_REG_CTRL2,
719 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
720 },
721 .attribute_group = {
722 .attrs = pcf2127_attrs,
723 },
636 },
637 [PCF2129] = {
638 .type = PCF2129,
639 .max_register = 0x19,
640 .has_nvmem = 0,
641 .has_bit_wd_ctl_cd0 = 0,
642 .reg_time_base = PCF2127_REG_TIME_BASE,
643 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
644 .reg_wd_ctl = PCF2127_REG_WD_CTL,
645 .reg_wd_val = PCF2127_REG_WD_VAL,
646 .reg_clkout = PCF2127_REG_CLKOUT,
724 },
725 [PCF2129] = {
726 .type = PCF2129,
727 .max_register = 0x19,
728 .has_nvmem = 0,
729 .has_bit_wd_ctl_cd0 = 0,
730 .reg_time_base = PCF2127_REG_TIME_BASE,
731 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
732 .reg_wd_ctl = PCF2127_REG_WD_CTL,
733 .reg_wd_val = PCF2127_REG_WD_VAL,
734 .reg_clkout = PCF2127_REG_CLKOUT,
735 .ts_count = 1,
736 .ts[0] = {
737 .reg_base = PCF2127_REG_TS1_BASE,
738 .gnd_detect_reg = PCF2127_REG_CTRL1,
739 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
740 .inter_detect_reg = PCF2127_REG_CTRL2,
741 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
742 .ie_reg = PCF2127_REG_CTRL2,
743 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
744 },
745 .attribute_group = {
746 .attrs = pcf2127_attrs,
747 },
647 },
648};
649
748 },
749};
750
751/*
752 * Enable timestamp function and corresponding interrupt(s).
753 */
754static int pcf2127_enable_ts(struct device *dev, int ts_id)
755{
756 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
757 int ret;
758
759 if (ts_id >= pcf2127->cfg->ts_count) {
760 dev_err(dev, "%s: invalid tamper detection ID (%d)\n",
761 __func__, ts_id);
762 return -EINVAL;
763 }
764
765 /* Enable timestamp function. */
766 ret = regmap_update_bits(pcf2127->regmap,
767 pcf2127->cfg->ts[ts_id].reg_base,
768 PCF2127_BIT_TS_CTRL_TSOFF |
769 PCF2127_BIT_TS_CTRL_TSM,
770 PCF2127_BIT_TS_CTRL_TSM);
771 if (ret) {
772 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n",
773 __func__, ts_id);
774 return ret;
775 }
776
777 /* TS input pin driven to GND detection is supported by all variants.
778 * Make sure that interrupt bit is defined.
779 */
780 if (pcf2127->cfg->ts[ts_id].gnd_detect_bit == 0) {
781 dev_err(dev, "%s: tamper detection to GND configuration invalid\n",
782 __func__);
783 return ret;
784 }
785
786 /*
787 * Enable interrupt generation when TSF timestamp flag is set.
788 * Interrupt signals are open-drain outputs and can be left floating if
789 * unused.
790 */
791 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg,
792 pcf2127->cfg->ts[ts_id].ie_bit,
793 pcf2127->cfg->ts[ts_id].ie_bit);
794 if (ret) {
795 dev_err(dev, "%s: tamper detection TSIE%d config failed\n",
796 __func__, ts_id);
797 return ret;
798 }
799
800 return ret;
801}
802
650static int pcf2127_probe(struct device *dev, struct regmap *regmap,
651 int alarm_irq, const char *name, const struct pcf21xx_config *config)
652{
653 struct pcf2127 *pcf2127;
654 int ret = 0;
655 unsigned int val;
656
657 dev_dbg(dev, "%s\n", __func__);

--- 114 unchanged lines hidden (view full) ---

772 PCF2127_BIT_CTRL3_BLIE, 0);
773 if (ret) {
774 dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
775 __func__);
776 return ret;
777 }
778
779 /*
803static int pcf2127_probe(struct device *dev, struct regmap *regmap,
804 int alarm_irq, const char *name, const struct pcf21xx_config *config)
805{
806 struct pcf2127 *pcf2127;
807 int ret = 0;
808 unsigned int val;
809
810 dev_dbg(dev, "%s\n", __func__);

--- 114 unchanged lines hidden (view full) ---

925 PCF2127_BIT_CTRL3_BLIE, 0);
926 if (ret) {
927 dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
928 __func__);
929 return ret;
930 }
931
932 /*
780 * Enable timestamp function and store timestamp of first trigger
781 * event until TSF1 and TSF2 interrupt flags are cleared.
933 * Enable timestamp functions 1 to 4.
782 */
934 */
783 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL,
784 PCF2127_BIT_TS_CTRL_TSOFF |
785 PCF2127_BIT_TS_CTRL_TSM,
786 PCF2127_BIT_TS_CTRL_TSM);
787 if (ret) {
788 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n",
789 __func__);
790 return ret;
935 for (int i = 0; i < pcf2127->cfg->ts_count; i++) {
936 ret = pcf2127_enable_ts(dev, i);
937 if (ret)
938 return ret;
791 }
792
939 }
940
793 /*
794 * Enable interrupt generation when TSF1 or TSF2 timestamp flags
795 * are set. Interrupt signal is an open-drain output and can be
796 * left floating if unused.
797 */
798 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
799 PCF2127_BIT_CTRL2_TSIE,
800 PCF2127_BIT_CTRL2_TSIE);
941 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group);
801 if (ret) {
942 if (ret) {
802 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n",
803 __func__);
804 return ret;
805 }
806
807 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group);
808 if (ret) {
809 dev_err(dev, "%s: tamper sysfs registering failed\n",
810 __func__);
811 return ret;
812 }
813
814 return devm_rtc_register_device(pcf2127->rtc);
815}
816

--- 279 unchanged lines hidden --- 		943 dev_err(dev, "%s: tamper sysfs registering failed\n",
944 __func__);
945 return ret;
946 }
947
948 return devm_rtc_register_device(pcf2127->rtc);
949}
950

--- 279 unchanged lines hidden ---