rtc-pcf2127.c (7c6f0db41ab5fbd7ee3a2f9880ac23509a5d55d1) rtc-pcf2127.c (6b57ec29e3fc31d43e672f6fede5d4a76140308b)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An I2C and SPI driver for the NXP PCF2127/29 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions

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94
95struct pcf21xx_config {
96 int type; /* IC variant */
97 int max_register;
98 unsigned int has_nvmem:1;
99 unsigned int has_bit_wd_ctl_cd0:1;
100 u8 reg_time_base; /* Time/date base register. */
101 u8 regs_alarm_base; /* Alarm function base registers. */
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An I2C and SPI driver for the NXP PCF2127/29 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions

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94
95struct pcf21xx_config {
96 int type; /* IC variant */
97 int max_register;
98 unsigned int has_nvmem:1;
99 unsigned int has_bit_wd_ctl_cd0:1;
100 u8 reg_time_base; /* Time/date base register. */
101 u8 regs_alarm_base; /* Alarm function base registers. */
102 u8 reg_wd_ctl; /* Watchdog control register. */
103 u8 reg_wd_val; /* Watchdog value register. */
102};
103
104struct pcf2127 {
105 struct rtc_device *rtc;
106 struct watchdog_device wdd;
107 struct regmap *regmap;
108 const struct pcf21xx_config *cfg;
109 time64_t ts;

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264}
265
266/* watchdog driver */
267
268static int pcf2127_wdt_ping(struct watchdog_device *wdd)
269{
270 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
271
104};
105
106struct pcf2127 {
107 struct rtc_device *rtc;
108 struct watchdog_device wdd;
109 struct regmap *regmap;
110 const struct pcf21xx_config *cfg;
111 time64_t ts;

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266}
267
268/* watchdog driver */
269
270static int pcf2127_wdt_ping(struct watchdog_device *wdd)
271{
272 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
273
272 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout);
274 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeout);
273}
274
275/*
276 * Restart watchdog timer if feature is active.
277 *
278 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
279 * since register also contain control/status flags for other features.
280 * Always call this function after reading CTRL2 register.

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298{
299 return pcf2127_wdt_ping(wdd);
300}
301
302static int pcf2127_wdt_stop(struct watchdog_device *wdd)
303{
304 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
305
275}
276
277/*
278 * Restart watchdog timer if feature is active.
279 *
280 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
281 * since register also contain control/status flags for other features.
282 * Always call this function after reading CTRL2 register.

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300{
301 return pcf2127_wdt_ping(wdd);
302}
303
304static int pcf2127_wdt_stop(struct watchdog_device *wdd)
305{
306 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
307
306 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL,
308 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
307 PCF2127_WD_VAL_STOP);
308}
309
310static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
311 unsigned int new_timeout)
312{
313 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
314 new_timeout, wdd->timeout);

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347 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX;
348 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT;
349 pcf2127->wdd.min_hw_heartbeat_ms = 500;
350 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
351
352 watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
353
354 /* Test if watchdog timer is started by bootloader */
309 PCF2127_WD_VAL_STOP);
310}
311
312static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
313 unsigned int new_timeout)
314{
315 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
316 new_timeout, wdd->timeout);

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349 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX;
350 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT;
351 pcf2127->wdd.min_hw_heartbeat_ms = 500;
352 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
353
354 watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
355
356 /* Test if watchdog timer is started by bootloader */
355 ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout);
357 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout);
356 if (ret)
357 return ret;
358
359 if (wdd_timeout)
360 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
361
362 return devm_watchdog_register_device(dev, &pcf2127->wdd);
363}

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622static struct pcf21xx_config pcf21xx_cfg[] = {
623 [PCF2127] = {
624 .type = PCF2127,
625 .max_register = 0x1d,
626 .has_nvmem = 1,
627 .has_bit_wd_ctl_cd0 = 1,
628 .reg_time_base = PCF2127_REG_TIME_BASE,
629 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
358 if (ret)
359 return ret;
360
361 if (wdd_timeout)
362 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
363
364 return devm_watchdog_register_device(dev, &pcf2127->wdd);
365}

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624static struct pcf21xx_config pcf21xx_cfg[] = {
625 [PCF2127] = {
626 .type = PCF2127,
627 .max_register = 0x1d,
628 .has_nvmem = 1,
629 .has_bit_wd_ctl_cd0 = 1,
630 .reg_time_base = PCF2127_REG_TIME_BASE,
631 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
632 .reg_wd_ctl = PCF2127_REG_WD_CTL,
633 .reg_wd_val = PCF2127_REG_WD_VAL,
630 },
631 [PCF2129] = {
632 .type = PCF2129,
633 .max_register = 0x19,
634 .has_nvmem = 0,
635 .has_bit_wd_ctl_cd0 = 0,
636 .reg_time_base = PCF2127_REG_TIME_BASE,
637 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
634 },
635 [PCF2129] = {
636 .type = PCF2129,
637 .max_register = 0x19,
638 .has_nvmem = 0,
639 .has_bit_wd_ctl_cd0 = 0,
640 .reg_time_base = PCF2127_REG_TIME_BASE,
641 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
642 .reg_wd_ctl = PCF2127_REG_WD_CTL,
643 .reg_wd_val = PCF2127_REG_WD_VAL,
638 },
639};
640
641static int pcf2127_probe(struct device *dev, struct regmap *regmap,
642 int alarm_irq, const char *name, const struct pcf21xx_config *config)
643{
644 struct pcf2127 *pcf2127;
645 int ret = 0;

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731 * Watchdog timer enabled and reset pin /RST activated when timed out.
732 * Select 1Hz clock source for watchdog timer.
733 * Note: Countdown timer disabled and not available.
734 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
735 * of register watchdg_tim_ctl. The bit[6] is labeled
736 * as T. Bits labeled as T must always be written with
737 * logic 0.
738 */
644 },
645};
646
647static int pcf2127_probe(struct device *dev, struct regmap *regmap,
648 int alarm_irq, const char *name, const struct pcf21xx_config *config)
649{
650 struct pcf2127 *pcf2127;
651 int ret = 0;

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737 * Watchdog timer enabled and reset pin /RST activated when timed out.
738 * Select 1Hz clock source for watchdog timer.
739 * Note: Countdown timer disabled and not available.
740 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
741 * of register watchdg_tim_ctl. The bit[6] is labeled
742 * as T. Bits labeled as T must always be written with
743 * logic 0.
744 */
739 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
745 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl,
740 PCF2127_BIT_WD_CTL_CD1 |
741 PCF2127_BIT_WD_CTL_CD0 |
742 PCF2127_BIT_WD_CTL_TF1 |
743 PCF2127_BIT_WD_CTL_TF0,
744 PCF2127_BIT_WD_CTL_CD1 |
745 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) |
746 PCF2127_BIT_WD_CTL_TF1);
747 if (ret) {

--- 339 unchanged lines hidden --- 		746 PCF2127_BIT_WD_CTL_CD1 |
747 PCF2127_BIT_WD_CTL_CD0 |
748 PCF2127_BIT_WD_CTL_TF1 |
749 PCF2127_BIT_WD_CTL_TF0,
750 PCF2127_BIT_WD_CTL_CD1 |
751 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) |
752 PCF2127_BIT_WD_CTL_TF1);
753 if (ret) {

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