rtc-pcf2127.c (420cc9e850dbc8e6ea7dd1e53d62d64cd8766354) rtc-pcf2127.c (afc505bf9039caf5a377d8b9705ef42f6d4ac7d4)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An I2C and SPI driver for the NXP PCF2127/29 RTC
3 * An I2C and SPI driver for the NXP PCF2127/29/31 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions
9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com>
10 *
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions
9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com>
10 *
11 * PCF2131 support
12 * Author: Hugo Villeneuve <hvilleneuve@dimonoff.com>
13 *
11 * based on the other drivers in this same directory.
12 *
14 * based on the other drivers in this same directory.
15 *
13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
16 * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
17 * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf
14 */
15
16#include <linux/i2c.h>
17#include <linux/spi/spi.h>
18#include <linux/bcd.h>
19#include <linux/rtc.h>
20#include <linux/slab.h>
21#include <linux/module.h>

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62/* Tamper timestamp1 registers */
63#define PCF2127_REG_TS1_BASE 0x12
64#define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
65#define PCF2127_BIT_TS_CTRL_TSM BIT(7)
66/*
67 * RAM registers
68 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
69 * battery backed and can survive a power outage.
18 */
19
20#include <linux/i2c.h>
21#include <linux/spi/spi.h>
22#include <linux/bcd.h>
23#include <linux/rtc.h>
24#include <linux/slab.h>
25#include <linux/module.h>

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66/* Tamper timestamp1 registers */
67#define PCF2127_REG_TS1_BASE 0x12
68#define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
69#define PCF2127_BIT_TS_CTRL_TSM BIT(7)
70/*
71 * RAM registers
72 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
73 * battery backed and can survive a power outage.
70 * PCF2129 doesn't have this feature.
74 * PCF2129/31 doesn't have this feature.
71 */
72#define PCF2127_REG_RAM_ADDR_MSB 0x1A
73#define PCF2127_REG_RAM_WRT_CMD 0x1C
74#define PCF2127_REG_RAM_RD_CMD 0x1D
75
76/* Watchdog timer value constants */
77#define PCF2127_WD_VAL_STOP 0
78#define PCF2127_WD_VAL_MIN 2
79#define PCF2127_WD_VAL_MAX 255
80#define PCF2127_WD_VAL_DEFAULT 60
81
82/* Mask for currently enabled interrupts */
83#define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
84#define PCF2127_CTRL2_IRQ_MASK ( \
85 PCF2127_BIT_CTRL2_AF | \
86 PCF2127_BIT_CTRL2_WDTF | \
87 PCF2127_BIT_CTRL2_TSF2)
88
75 */
76#define PCF2127_REG_RAM_ADDR_MSB 0x1A
77#define PCF2127_REG_RAM_WRT_CMD 0x1C
78#define PCF2127_REG_RAM_RD_CMD 0x1D
79
80/* Watchdog timer value constants */
81#define PCF2127_WD_VAL_STOP 0
82#define PCF2127_WD_VAL_MIN 2
83#define PCF2127_WD_VAL_MAX 255
84#define PCF2127_WD_VAL_DEFAULT 60
85
86/* Mask for currently enabled interrupts */
87#define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
88#define PCF2127_CTRL2_IRQ_MASK ( \
89 PCF2127_BIT_CTRL2_AF | \
90 PCF2127_BIT_CTRL2_WDTF | \
91 PCF2127_BIT_CTRL2_TSF2)
92
89#define PCF2127_MAX_TS_SUPPORTED 1
93#define PCF2127_MAX_TS_SUPPORTED 4
90
94
95/* Control register 4 */
96#define PCF2131_REG_CTRL4 0x03
97#define PCF2131_BIT_CTRL4_TSF4 BIT(4)
98#define PCF2131_BIT_CTRL4_TSF3 BIT(5)
99#define PCF2131_BIT_CTRL4_TSF2 BIT(6)
100#define PCF2131_BIT_CTRL4_TSF1 BIT(7)
101/* Control register 5 */
102#define PCF2131_REG_CTRL5 0x04
103#define PCF2131_BIT_CTRL5_TSIE4 BIT(4)
104#define PCF2131_BIT_CTRL5_TSIE3 BIT(5)
105#define PCF2131_BIT_CTRL5_TSIE2 BIT(6)
106#define PCF2131_BIT_CTRL5_TSIE1 BIT(7)
107/* Software reset register */
108#define PCF2131_REG_SR_RESET 0x05
109#define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5))
110#define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7))
111/* Time and date registers */
112#define PCF2131_REG_TIME_BASE 0x07
113/* Alarm registers */
114#define PCF2131_REG_ALARM_BASE 0x0E
115/* CLKOUT control register */
116#define PCF2131_REG_CLKOUT 0x13
117/* Watchdog registers */
118#define PCF2131_REG_WD_CTL 0x35
119#define PCF2131_REG_WD_VAL 0x36
120/* Tamper timestamp1 registers */
121#define PCF2131_REG_TS1_BASE 0x14
122/* Tamper timestamp2 registers */
123#define PCF2131_REG_TS2_BASE 0x1B
124/* Tamper timestamp3 registers */
125#define PCF2131_REG_TS3_BASE 0x22
126/* Tamper timestamp4 registers */
127#define PCF2131_REG_TS4_BASE 0x29
128/* Interrupt mask registers */
129#define PCF2131_REG_INT_A_MASK1 0x31
130#define PCF2131_REG_INT_A_MASK2 0x32
131#define PCF2131_REG_INT_B_MASK1 0x33
132#define PCF2131_REG_INT_B_MASK2 0x34
133#define PCF2131_BIT_INT_BLIE BIT(0)
134#define PCF2131_BIT_INT_BIE BIT(1)
135#define PCF2131_BIT_INT_AIE BIT(2)
136#define PCF2131_BIT_INT_WD_CD BIT(3)
137#define PCF2131_BIT_INT_SI BIT(4)
138#define PCF2131_BIT_INT_MI BIT(5)
139#define PCF2131_CTRL2_IRQ_MASK ( \
140 PCF2127_BIT_CTRL2_AF | \
141 PCF2127_BIT_CTRL2_WDTF)
142#define PCF2131_CTRL4_IRQ_MASK ( \
143 PCF2131_BIT_CTRL4_TSF4 | \
144 PCF2131_BIT_CTRL4_TSF3 | \
145 PCF2131_BIT_CTRL4_TSF2 | \
146 PCF2131_BIT_CTRL4_TSF1)
147
91enum pcf21xx_type {
92 PCF2127,
93 PCF2129,
148enum pcf21xx_type {
149 PCF2127,
150 PCF2129,
151 PCF2131,
94 PCF21XX_LAST_ID
95};
96
97struct pcf21xx_ts_config {
98 u8 reg_base; /* Base register to read timestamp values. */
99
100 /*
101 * If the TS input pin is driven to GND, an interrupt can be generated

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525 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id);
526 if (!ret)
527 pcf2127->ts_valid[ts_id] = true;
528}
529
530static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
531{
532 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
152 PCF21XX_LAST_ID
153};
154
155struct pcf21xx_ts_config {
156 u8 reg_base; /* Base register to read timestamp values. */
157
158 /*
159 * If the TS input pin is driven to GND, an interrupt can be generated

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583 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id);
584 if (!ret)
585 pcf2127->ts_valid[ts_id] = true;
586}
587
588static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
589{
590 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
533 unsigned int ctrl1, ctrl2;
591 unsigned int ctrl2;
534 int ret = 0;
535
592 int ret = 0;
593
536 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
537 if (ret)
538 return IRQ_NONE;
539
540 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
541 if (ret)
542 return IRQ_NONE;
543
594 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
595 if (ret)
596 return IRQ_NONE;
597
544 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
545 return IRQ_NONE;
598 if (pcf2127->cfg->ts_count == 1) {
599 /* PCF2127/29 */
600 unsigned int ctrl1;
546
601
547 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
548 pcf2127_rtc_ts_snapshot(dev, 0);
602 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
603 if (ret)
604 return IRQ_NONE;
549
605
550 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
551 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
552 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
606 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
607 return IRQ_NONE;
553
608
554 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
555 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
556 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
609 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
610 pcf2127_rtc_ts_snapshot(dev, 0);
557
611
612 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
613 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
614 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
615
616 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
617 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
618 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
619 } else {
620 /* PCF2131. */
621 unsigned int ctrl4;
622
623 ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4);
624 if (ret)
625 return IRQ_NONE;
626
627 if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK))
628 return IRQ_NONE;
629
630 if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) {
631 int i;
632 int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */
633
634 for (i = 0; i < pcf2127->cfg->ts_count; i++) {
635 if (ctrl4 & tsf_bit)
636 pcf2127_rtc_ts_snapshot(dev, i);
637
638 tsf_bit = tsf_bit >> 1;
639 }
640
641 regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4,
642 ctrl4 & ~PCF2131_CTRL4_IRQ_MASK);
643 }
644
645 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK)
646 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
647 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK);
648 }
649
558 if (ctrl2 & PCF2127_BIT_CTRL2_AF)
559 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
560
561 pcf2127_wdt_active_ping(&pcf2127->wdd);
562
563 return IRQ_HANDLED;
564}
565

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621
622static ssize_t timestamp0_store(struct device *dev,
623 struct device_attribute *attr,
624 const char *buf, size_t count)
625{
626 return timestamp_store(dev, attr, buf, count, 0);
627};
628
650 if (ctrl2 & PCF2127_BIT_CTRL2_AF)
651 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
652
653 pcf2127_wdt_active_ping(&pcf2127->wdd);
654
655 return IRQ_HANDLED;
656}
657

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713
714static ssize_t timestamp0_store(struct device *dev,
715 struct device_attribute *attr,
716 const char *buf, size_t count)
717{
718 return timestamp_store(dev, attr, buf, count, 0);
719};
720
721static ssize_t timestamp1_store(struct device *dev,
722 struct device_attribute *attr,
723 const char *buf, size_t count)
724{
725 return timestamp_store(dev, attr, buf, count, 1);
726};
727
728static ssize_t timestamp2_store(struct device *dev,
729 struct device_attribute *attr,
730 const char *buf, size_t count)
731{
732 return timestamp_store(dev, attr, buf, count, 2);
733};
734
735static ssize_t timestamp3_store(struct device *dev,
736 struct device_attribute *attr,
737 const char *buf, size_t count)
738{
739 return timestamp_store(dev, attr, buf, count, 3);
740};
741
629static ssize_t timestamp_show(struct device *dev,
630 struct device_attribute *attr, char *buf,
631 int ts_id)
632{
633 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
634 int ret;
635 time64_t ts;
636

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685}
686
687static ssize_t timestamp0_show(struct device *dev,
688 struct device_attribute *attr, char *buf)
689{
690 return timestamp_show(dev, attr, buf, 0);
691};
692
742static ssize_t timestamp_show(struct device *dev,
743 struct device_attribute *attr, char *buf,
744 int ts_id)
745{
746 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
747 int ret;
748 time64_t ts;
749

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798}
799
800static ssize_t timestamp0_show(struct device *dev,
801 struct device_attribute *attr, char *buf)
802{
803 return timestamp_show(dev, attr, buf, 0);
804};
805
806static ssize_t timestamp1_show(struct device *dev,
807 struct device_attribute *attr, char *buf)
808{
809 return timestamp_show(dev, attr, buf, 1);
810};
811
812static ssize_t timestamp2_show(struct device *dev,
813 struct device_attribute *attr, char *buf)
814{
815 return timestamp_show(dev, attr, buf, 2);
816};
817
818static ssize_t timestamp3_show(struct device *dev,
819 struct device_attribute *attr, char *buf)
820{
821 return timestamp_show(dev, attr, buf, 3);
822};
823
693static DEVICE_ATTR_RW(timestamp0);
824static DEVICE_ATTR_RW(timestamp0);
825static DEVICE_ATTR_RW(timestamp1);
826static DEVICE_ATTR_RW(timestamp2);
827static DEVICE_ATTR_RW(timestamp3);
694
695static struct attribute *pcf2127_attrs[] = {
696 &dev_attr_timestamp0.attr,
697 NULL
698};
699
828
829static struct attribute *pcf2127_attrs[] = {
830 &dev_attr_timestamp0.attr,
831 NULL
832};
833
834static struct attribute *pcf2131_attrs[] = {
835 &dev_attr_timestamp0.attr,
836 &dev_attr_timestamp1.attr,
837 &dev_attr_timestamp2.attr,
838 &dev_attr_timestamp3.attr,
839 NULL
840};
841
700static struct pcf21xx_config pcf21xx_cfg[] = {
701 [PCF2127] = {
702 .type = PCF2127,
703 .max_register = 0x1d,
704 .has_nvmem = 1,
705 .has_bit_wd_ctl_cd0 = 1,
706 .reg_time_base = PCF2127_REG_TIME_BASE,
707 .regs_alarm_base = PCF2127_REG_ALARM_BASE,

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741 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
742 .ie_reg = PCF2127_REG_CTRL2,
743 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
744 },
745 .attribute_group = {
746 .attrs = pcf2127_attrs,
747 },
748 },
842static struct pcf21xx_config pcf21xx_cfg[] = {
843 [PCF2127] = {
844 .type = PCF2127,
845 .max_register = 0x1d,
846 .has_nvmem = 1,
847 .has_bit_wd_ctl_cd0 = 1,
848 .reg_time_base = PCF2127_REG_TIME_BASE,
849 .regs_alarm_base = PCF2127_REG_ALARM_BASE,

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883 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
884 .ie_reg = PCF2127_REG_CTRL2,
885 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
886 },
887 .attribute_group = {
888 .attrs = pcf2127_attrs,
889 },
890 },
891 [PCF2131] = {
892 .type = PCF2131,
893 .max_register = 0x36,
894 .has_nvmem = 0,
895 .has_bit_wd_ctl_cd0 = 0,
896 .reg_time_base = PCF2131_REG_TIME_BASE,
897 .regs_alarm_base = PCF2131_REG_ALARM_BASE,
898 .reg_wd_ctl = PCF2131_REG_WD_CTL,
899 .reg_wd_val = PCF2131_REG_WD_VAL,
900 .reg_clkout = PCF2131_REG_CLKOUT,
901 .ts_count = 4,
902 .ts[0] = {
903 .reg_base = PCF2131_REG_TS1_BASE,
904 .gnd_detect_reg = PCF2131_REG_CTRL4,
905 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1,
906 .inter_detect_bit = 0,
907 .ie_reg = PCF2131_REG_CTRL5,
908 .ie_bit = PCF2131_BIT_CTRL5_TSIE1,
909 },
910 .ts[1] = {
911 .reg_base = PCF2131_REG_TS2_BASE,
912 .gnd_detect_reg = PCF2131_REG_CTRL4,
913 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2,
914 .inter_detect_bit = 0,
915 .ie_reg = PCF2131_REG_CTRL5,
916 .ie_bit = PCF2131_BIT_CTRL5_TSIE2,
917 },
918 .ts[2] = {
919 .reg_base = PCF2131_REG_TS3_BASE,
920 .gnd_detect_reg = PCF2131_REG_CTRL4,
921 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3,
922 .inter_detect_bit = 0,
923 .ie_reg = PCF2131_REG_CTRL5,
924 .ie_bit = PCF2131_BIT_CTRL5_TSIE3,
925 },
926 .ts[3] = {
927 .reg_base = PCF2131_REG_TS4_BASE,
928 .gnd_detect_reg = PCF2131_REG_CTRL4,
929 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4,
930 .inter_detect_bit = 0,
931 .ie_reg = PCF2131_REG_CTRL5,
932 .ie_bit = PCF2131_BIT_CTRL5_TSIE4,
933 },
934 .attribute_group = {
935 .attrs = pcf2131_attrs,
936 },
937 },
749};
750
751/*
752 * Enable timestamp function and corresponding interrupt(s).
753 */
754static int pcf2127_enable_ts(struct device *dev, int ts_id)
755{
756 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);

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888
889 msleep(100);
890 }
891
892 /*
893 * Watchdog timer enabled and reset pin /RST activated when timed out.
894 * Select 1Hz clock source for watchdog timer.
895 * Note: Countdown timer disabled and not available.
938};
939
940/*
941 * Enable timestamp function and corresponding interrupt(s).
942 */
943static int pcf2127_enable_ts(struct device *dev, int ts_id)
944{
945 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);

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1077
1078 msleep(100);
1079 }
1080
1081 /*
1082 * Watchdog timer enabled and reset pin /RST activated when timed out.
1083 * Select 1Hz clock source for watchdog timer.
1084 * Note: Countdown timer disabled and not available.
896 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
1085 * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD
897 * of register watchdg_tim_ctl. The bit[6] is labeled
898 * as T. Bits labeled as T must always be written with
899 * logic 0.
900 */
901 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl,
902 PCF2127_BIT_WD_CTL_CD1 |
903 PCF2127_BIT_WD_CTL_CD0 |
904 PCF2127_BIT_WD_CTL_TF1 |

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948 return devm_rtc_register_device(pcf2127->rtc);
949}
950
951#ifdef CONFIG_OF
952static const struct of_device_id pcf2127_of_match[] = {
953 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] },
954 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] },
955 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] },
1086 * of register watchdg_tim_ctl. The bit[6] is labeled
1087 * as T. Bits labeled as T must always be written with
1088 * logic 0.
1089 */
1090 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl,
1091 PCF2127_BIT_WD_CTL_CD1 |
1092 PCF2127_BIT_WD_CTL_CD0 |
1093 PCF2127_BIT_WD_CTL_TF1 |

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1137 return devm_rtc_register_device(pcf2127->rtc);
1138}
1139
1140#ifdef CONFIG_OF
1141static const struct of_device_id pcf2127_of_match[] = {
1142 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] },
1143 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] },
1144 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] },
1145 { .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] },
956 {}
957};
958MODULE_DEVICE_TABLE(of, pcf2127_of_match);
959#endif
960
961#if IS_ENABLED(CONFIG_I2C)
962
963static int pcf2127_i2c_write(void *context, const void *data, size_t count)

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1035};
1036
1037static struct i2c_driver pcf2127_i2c_driver;
1038
1039static const struct i2c_device_id pcf2127_i2c_id[] = {
1040 { "pcf2127", PCF2127 },
1041 { "pcf2129", PCF2129 },
1042 { "pca2129", PCF2129 },
1146 {}
1147};
1148MODULE_DEVICE_TABLE(of, pcf2127_of_match);
1149#endif
1150
1151#if IS_ENABLED(CONFIG_I2C)
1152
1153static int pcf2127_i2c_write(void *context, const void *data, size_t count)

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1225};
1226
1227static struct i2c_driver pcf2127_i2c_driver;
1228
1229static const struct i2c_device_id pcf2127_i2c_id[] = {
1230 { "pcf2127", PCF2127 },
1231 { "pcf2129", PCF2129 },
1232 { "pca2129", PCF2129 },
1233 { "pcf2131", PCF2131 },
1043 { }
1044};
1045MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
1046
1047static int pcf2127_i2c_probe(struct i2c_client *client)
1048{
1049 struct regmap *regmap;
1050 static struct regmap_config config = {

--- 105 unchanged lines hidden (view full) ---

1156 pcf2127_spi_driver.driver.name,
1157 variant);
1158}
1159
1160static const struct spi_device_id pcf2127_spi_id[] = {
1161 { "pcf2127", PCF2127 },
1162 { "pcf2129", PCF2129 },
1163 { "pca2129", PCF2129 },
1234 { }
1235};
1236MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
1237
1238static int pcf2127_i2c_probe(struct i2c_client *client)
1239{
1240 struct regmap *regmap;
1241 static struct regmap_config config = {

--- 105 unchanged lines hidden (view full) ---

1347 pcf2127_spi_driver.driver.name,
1348 variant);
1349}
1350
1351static const struct spi_device_id pcf2127_spi_id[] = {
1352 { "pcf2127", PCF2127 },
1353 { "pcf2129", PCF2129 },
1354 { "pca2129", PCF2129 },
1355 { "pcf2131", PCF2131 },
1164 { }
1165};
1166MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
1167
1168static struct spi_driver pcf2127_spi_driver = {
1169 .driver = {
1170 .name = "rtc-pcf2127-spi",
1171 .of_match_table = of_match_ptr(pcf2127_of_match),

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1220static void __exit pcf2127_exit(void)
1221{
1222 pcf2127_spi_unregister_driver();
1223 pcf2127_i2c_unregister_driver();
1224}
1225module_exit(pcf2127_exit)
1226
1227MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
1356 { }
1357};
1358MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
1359
1360static struct spi_driver pcf2127_spi_driver = {
1361 .driver = {
1362 .name = "rtc-pcf2127-spi",
1363 .of_match_table = of_match_ptr(pcf2127_of_match),

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1412static void __exit pcf2127_exit(void)
1413{
1414 pcf2127_spi_unregister_driver();
1415 pcf2127_i2c_unregister_driver();
1416}
1417module_exit(pcf2127_exit)
1418
1419MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
1228MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
1420MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver");
1229MODULE_LICENSE("GPL v2");
1421MODULE_LICENSE("GPL v2");