pinctrl-rza2.c (cbecf716ca618fd44feda6bd9a64a8179d031fc5) pinctrl-rza2.c (8a8d6bbe1d3bc7137c777ba06246d7e9c08dde4d)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
4 *
5 * Copyright (C) 2018 Chris Brandt
6 */
7
8/*

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235
236static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
237{
238 struct device_node *np = priv->dev->of_node;
239 struct of_phandle_args of_args;
240 int ret;
241
242 chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
4 *
5 * Copyright (C) 2018 Chris Brandt
6 */
7
8/*

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235
236static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
237{
238 struct device_node *np = priv->dev->of_node;
239 struct of_phandle_args of_args;
240 int ret;
241
242 chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
243 chip.of_node = np;
244 chip.parent = priv->dev;
245 chip.ngpio = priv->npins;
246
247 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
248 &of_args);
249 if (ret) {
250 dev_err(priv->dev, "Unable to parse gpio-ranges\n");
251 return ret;

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243 chip.parent = priv->dev;
244 chip.ngpio = priv->npins;
245
246 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
247 &of_args);
248 if (ret) {
249 dev_err(priv->dev, "Unable to parse gpio-ranges\n");
250 return ret;

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