pinctrl-ocelot.c (8632987380765dee716d460640aa58d58d52998e) pinctrl-ocelot.c (8a8d6bbe1d3bc7137c777ba06246d7e9c08dde4d)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */

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52#define OCELOT_GPIO_INTR_IDENT 0x1c
53#define OCELOT_GPIO_ALT0 0x20
54#define OCELOT_GPIO_ALT1 0x24
55#define OCELOT_GPIO_SD_MAP 0x28
56
57#define OCELOT_FUNC_PER_PIN 4
58
59enum {
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */

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52#define OCELOT_GPIO_INTR_IDENT 0x1c
53#define OCELOT_GPIO_ALT0 0x20
54#define OCELOT_GPIO_ALT1 0x24
55#define OCELOT_GPIO_SD_MAP 0x28
56
57#define OCELOT_FUNC_PER_PIN 4
58
59enum {
60 FUNC_CAN0_a,
61 FUNC_CAN0_b,
62 FUNC_CAN1,
60 FUNC_NONE,
63 FUNC_NONE,
64 FUNC_FC0_a,
65 FUNC_FC0_b,
66 FUNC_FC0_c,
67 FUNC_FC1_a,
68 FUNC_FC1_b,
69 FUNC_FC1_c,
70 FUNC_FC2_a,
71 FUNC_FC2_b,
72 FUNC_FC3_a,
73 FUNC_FC3_b,
74 FUNC_FC3_c,
75 FUNC_FC4_a,
76 FUNC_FC4_b,
77 FUNC_FC4_c,
78 FUNC_FC_SHRD0,
79 FUNC_FC_SHRD1,
80 FUNC_FC_SHRD2,
81 FUNC_FC_SHRD3,
82 FUNC_FC_SHRD4,
83 FUNC_FC_SHRD5,
84 FUNC_FC_SHRD6,
85 FUNC_FC_SHRD7,
86 FUNC_FC_SHRD8,
87 FUNC_FC_SHRD9,
88 FUNC_FC_SHRD10,
89 FUNC_FC_SHRD11,
90 FUNC_FC_SHRD12,
91 FUNC_FC_SHRD13,
92 FUNC_FC_SHRD14,
93 FUNC_FC_SHRD15,
94 FUNC_FC_SHRD16,
95 FUNC_FC_SHRD17,
96 FUNC_FC_SHRD18,
97 FUNC_FC_SHRD19,
98 FUNC_FC_SHRD20,
61 FUNC_GPIO,
99 FUNC_GPIO,
100 FUNC_IB_TRG_a,
101 FUNC_IB_TRG_b,
102 FUNC_IB_TRG_c,
62 FUNC_IRQ0,
103 FUNC_IRQ0,
104 FUNC_IRQ_IN_a,
105 FUNC_IRQ_IN_b,
106 FUNC_IRQ_IN_c,
63 FUNC_IRQ0_IN,
107 FUNC_IRQ0_IN,
108 FUNC_IRQ_OUT_a,
109 FUNC_IRQ_OUT_b,
110 FUNC_IRQ_OUT_c,
64 FUNC_IRQ0_OUT,
65 FUNC_IRQ1,
66 FUNC_IRQ1_IN,
67 FUNC_IRQ1_OUT,
68 FUNC_EXT_IRQ,
69 FUNC_MIIM,
111 FUNC_IRQ0_OUT,
112 FUNC_IRQ1,
113 FUNC_IRQ1_IN,
114 FUNC_IRQ1_OUT,
115 FUNC_EXT_IRQ,
116 FUNC_MIIM,
117 FUNC_MIIM_a,
118 FUNC_MIIM_b,
119 FUNC_MIIM_c,
120 FUNC_MIIM_Sa,
121 FUNC_MIIM_Sb,
122 FUNC_OB_TRG,
123 FUNC_OB_TRG_a,
124 FUNC_OB_TRG_b,
70 FUNC_PHY_LED,
71 FUNC_PCI_WAKE,
72 FUNC_MD,
73 FUNC_PTP0,
74 FUNC_PTP1,
75 FUNC_PTP2,
76 FUNC_PTP3,
125 FUNC_PHY_LED,
126 FUNC_PCI_WAKE,
127 FUNC_MD,
128 FUNC_PTP0,
129 FUNC_PTP1,
130 FUNC_PTP2,
131 FUNC_PTP3,
132 FUNC_PTPSYNC_1,
133 FUNC_PTPSYNC_2,
134 FUNC_PTPSYNC_3,
135 FUNC_PTPSYNC_4,
136 FUNC_PTPSYNC_5,
137 FUNC_PTPSYNC_6,
138 FUNC_PTPSYNC_7,
77 FUNC_PWM,
139 FUNC_PWM,
140 FUNC_QSPI1,
141 FUNC_QSPI2,
142 FUNC_R,
143 FUNC_RECO_a,
144 FUNC_RECO_b,
78 FUNC_RECO_CLK,
145 FUNC_RECO_CLK,
146 FUNC_SD,
79 FUNC_SFP,
147 FUNC_SFP,
148 FUNC_SFP_SD,
80 FUNC_SG0,
81 FUNC_SG1,
82 FUNC_SG2,
149 FUNC_SG0,
150 FUNC_SG1,
151 FUNC_SG2,
152 FUNC_SGPIO_a,
153 FUNC_SGPIO_b,
83 FUNC_SI,
84 FUNC_SI2,
85 FUNC_TACHO,
154 FUNC_SI,
155 FUNC_SI2,
156 FUNC_TACHO,
157 FUNC_TACHO_a,
158 FUNC_TACHO_b,
86 FUNC_TWI,
87 FUNC_TWI2,
88 FUNC_TWI3,
89 FUNC_TWI_SCL_M,
159 FUNC_TWI,
160 FUNC_TWI2,
161 FUNC_TWI3,
162 FUNC_TWI_SCL_M,
163 FUNC_TWI_SLC_GATE,
164 FUNC_TWI_SLC_GATE_AD,
90 FUNC_UART,
91 FUNC_UART2,
92 FUNC_UART3,
165 FUNC_UART,
166 FUNC_UART2,
167 FUNC_UART3,
168 FUNC_USB_H_a,
169 FUNC_USB_H_b,
170 FUNC_USB_H_c,
171 FUNC_USB_S_a,
172 FUNC_USB_S_b,
173 FUNC_USB_S_c,
93 FUNC_PLL_STAT,
94 FUNC_EMMC,
174 FUNC_PLL_STAT,
175 FUNC_EMMC,
176 FUNC_EMMC_SD,
95 FUNC_REF_CLK,
96 FUNC_RCVRD_CLK,
97 FUNC_MAX
98};
99
100static const char *const ocelot_function_names[] = {
177 FUNC_REF_CLK,
178 FUNC_RCVRD_CLK,
179 FUNC_MAX
180};
181
182static const char *const ocelot_function_names[] = {
183 [FUNC_CAN0_a] = "can0_a",
184 [FUNC_CAN0_b] = "can0_b",
185 [FUNC_CAN1] = "can1",
101 [FUNC_NONE] = "none",
186 [FUNC_NONE] = "none",
187 [FUNC_FC0_a] = "fc0_a",
188 [FUNC_FC0_b] = "fc0_b",
189 [FUNC_FC0_c] = "fc0_c",
190 [FUNC_FC1_a] = "fc1_a",
191 [FUNC_FC1_b] = "fc1_b",
192 [FUNC_FC1_c] = "fc1_c",
193 [FUNC_FC2_a] = "fc2_a",
194 [FUNC_FC2_b] = "fc2_b",
195 [FUNC_FC3_a] = "fc3_a",
196 [FUNC_FC3_b] = "fc3_b",
197 [FUNC_FC3_c] = "fc3_c",
198 [FUNC_FC4_a] = "fc4_a",
199 [FUNC_FC4_b] = "fc4_b",
200 [FUNC_FC4_c] = "fc4_c",
201 [FUNC_FC_SHRD0] = "fc_shrd0",
202 [FUNC_FC_SHRD1] = "fc_shrd1",
203 [FUNC_FC_SHRD2] = "fc_shrd2",
204 [FUNC_FC_SHRD3] = "fc_shrd3",
205 [FUNC_FC_SHRD4] = "fc_shrd4",
206 [FUNC_FC_SHRD5] = "fc_shrd5",
207 [FUNC_FC_SHRD6] = "fc_shrd6",
208 [FUNC_FC_SHRD7] = "fc_shrd7",
209 [FUNC_FC_SHRD8] = "fc_shrd8",
210 [FUNC_FC_SHRD9] = "fc_shrd9",
211 [FUNC_FC_SHRD10] = "fc_shrd10",
212 [FUNC_FC_SHRD11] = "fc_shrd11",
213 [FUNC_FC_SHRD12] = "fc_shrd12",
214 [FUNC_FC_SHRD13] = "fc_shrd13",
215 [FUNC_FC_SHRD14] = "fc_shrd14",
216 [FUNC_FC_SHRD15] = "fc_shrd15",
217 [FUNC_FC_SHRD16] = "fc_shrd16",
218 [FUNC_FC_SHRD17] = "fc_shrd17",
219 [FUNC_FC_SHRD18] = "fc_shrd18",
220 [FUNC_FC_SHRD19] = "fc_shrd19",
221 [FUNC_FC_SHRD20] = "fc_shrd20",
102 [FUNC_GPIO] = "gpio",
222 [FUNC_GPIO] = "gpio",
223 [FUNC_IB_TRG_a] = "ib_trig_a",
224 [FUNC_IB_TRG_b] = "ib_trig_b",
225 [FUNC_IB_TRG_c] = "ib_trig_c",
103 [FUNC_IRQ0] = "irq0",
226 [FUNC_IRQ0] = "irq0",
227 [FUNC_IRQ_IN_a] = "irq_in_a",
228 [FUNC_IRQ_IN_b] = "irq_in_b",
229 [FUNC_IRQ_IN_c] = "irq_in_c",
104 [FUNC_IRQ0_IN] = "irq0_in",
230 [FUNC_IRQ0_IN] = "irq0_in",
231 [FUNC_IRQ_OUT_a] = "irq_out_a",
232 [FUNC_IRQ_OUT_b] = "irq_out_b",
233 [FUNC_IRQ_OUT_c] = "irq_out_c",
105 [FUNC_IRQ0_OUT] = "irq0_out",
106 [FUNC_IRQ1] = "irq1",
107 [FUNC_IRQ1_IN] = "irq1_in",
108 [FUNC_IRQ1_OUT] = "irq1_out",
109 [FUNC_EXT_IRQ] = "ext_irq",
110 [FUNC_MIIM] = "miim",
234 [FUNC_IRQ0_OUT] = "irq0_out",
235 [FUNC_IRQ1] = "irq1",
236 [FUNC_IRQ1_IN] = "irq1_in",
237 [FUNC_IRQ1_OUT] = "irq1_out",
238 [FUNC_EXT_IRQ] = "ext_irq",
239 [FUNC_MIIM] = "miim",
240 [FUNC_MIIM_a] = "miim_a",
241 [FUNC_MIIM_b] = "miim_b",
242 [FUNC_MIIM_c] = "miim_c",
243 [FUNC_MIIM_Sa] = "miim_slave_a",
244 [FUNC_MIIM_Sb] = "miim_slave_b",
111 [FUNC_PHY_LED] = "phy_led",
112 [FUNC_PCI_WAKE] = "pci_wake",
113 [FUNC_MD] = "md",
245 [FUNC_PHY_LED] = "phy_led",
246 [FUNC_PCI_WAKE] = "pci_wake",
247 [FUNC_MD] = "md",
248 [FUNC_OB_TRG] = "ob_trig",
249 [FUNC_OB_TRG_a] = "ob_trig_a",
250 [FUNC_OB_TRG_b] = "ob_trig_b",
114 [FUNC_PTP0] = "ptp0",
115 [FUNC_PTP1] = "ptp1",
116 [FUNC_PTP2] = "ptp2",
117 [FUNC_PTP3] = "ptp3",
251 [FUNC_PTP0] = "ptp0",
252 [FUNC_PTP1] = "ptp1",
253 [FUNC_PTP2] = "ptp2",
254 [FUNC_PTP3] = "ptp3",
255 [FUNC_PTPSYNC_1] = "ptpsync_1",
256 [FUNC_PTPSYNC_2] = "ptpsync_2",
257 [FUNC_PTPSYNC_3] = "ptpsync_3",
258 [FUNC_PTPSYNC_4] = "ptpsync_4",
259 [FUNC_PTPSYNC_5] = "ptpsync_5",
260 [FUNC_PTPSYNC_6] = "ptpsync_6",
261 [FUNC_PTPSYNC_7] = "ptpsync_7",
118 [FUNC_PWM] = "pwm",
262 [FUNC_PWM] = "pwm",
263 [FUNC_QSPI1] = "qspi1",
264 [FUNC_QSPI2] = "qspi2",
265 [FUNC_R] = "reserved",
266 [FUNC_RECO_a] = "reco_a",
267 [FUNC_RECO_b] = "reco_b",
119 [FUNC_RECO_CLK] = "reco_clk",
268 [FUNC_RECO_CLK] = "reco_clk",
269 [FUNC_SD] = "sd",
120 [FUNC_SFP] = "sfp",
270 [FUNC_SFP] = "sfp",
271 [FUNC_SFP_SD] = "sfp_sd",
121 [FUNC_SG0] = "sg0",
122 [FUNC_SG1] = "sg1",
123 [FUNC_SG2] = "sg2",
272 [FUNC_SG0] = "sg0",
273 [FUNC_SG1] = "sg1",
274 [FUNC_SG2] = "sg2",
275 [FUNC_SGPIO_a] = "sgpio_a",
276 [FUNC_SGPIO_b] = "sgpio_b",
124 [FUNC_SI] = "si",
125 [FUNC_SI2] = "si2",
126 [FUNC_TACHO] = "tacho",
277 [FUNC_SI] = "si",
278 [FUNC_SI2] = "si2",
279 [FUNC_TACHO] = "tacho",
280 [FUNC_TACHO_a] = "tacho_a",
281 [FUNC_TACHO_b] = "tacho_b",
127 [FUNC_TWI] = "twi",
128 [FUNC_TWI2] = "twi2",
129 [FUNC_TWI3] = "twi3",
130 [FUNC_TWI_SCL_M] = "twi_scl_m",
282 [FUNC_TWI] = "twi",
283 [FUNC_TWI2] = "twi2",
284 [FUNC_TWI3] = "twi3",
285 [FUNC_TWI_SCL_M] = "twi_scl_m",
286 [FUNC_TWI_SLC_GATE] = "twi_slc_gate",
287 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad",
288 [FUNC_USB_H_a] = "usb_host_a",
289 [FUNC_USB_H_b] = "usb_host_b",
290 [FUNC_USB_H_c] = "usb_host_c",
291 [FUNC_USB_S_a] = "usb_slave_a",
292 [FUNC_USB_S_b] = "usb_slave_b",
293 [FUNC_USB_S_c] = "usb_slave_c",
131 [FUNC_UART] = "uart",
132 [FUNC_UART2] = "uart2",
133 [FUNC_UART3] = "uart3",
134 [FUNC_PLL_STAT] = "pll_stat",
135 [FUNC_EMMC] = "emmc",
294 [FUNC_UART] = "uart",
295 [FUNC_UART2] = "uart2",
296 [FUNC_UART3] = "uart3",
297 [FUNC_PLL_STAT] = "pll_stat",
298 [FUNC_EMMC] = "emmc",
299 [FUNC_EMMC_SD] = "emmc_sd",
136 [FUNC_REF_CLK] = "ref_clk",
137 [FUNC_RCVRD_CLK] = "rcvrd_clk",
138};
139
140struct ocelot_pmx_func {
141 const char **groups;
142 unsigned int ngroups;
143};
144
145struct ocelot_pin_caps {
146 unsigned int pin;
147 unsigned char functions[OCELOT_FUNC_PER_PIN];
300 [FUNC_REF_CLK] = "ref_clk",
301 [FUNC_RCVRD_CLK] = "rcvrd_clk",
302};
303
304struct ocelot_pmx_func {
305 const char **groups;
306 unsigned int ngroups;
307};
308
309struct ocelot_pin_caps {
310 unsigned int pin;
311 unsigned char functions[OCELOT_FUNC_PER_PIN];
312 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */
148};
149
150struct ocelot_pinctrl {
151 struct device *dev;
152 struct pinctrl_dev *pctl;
153 struct gpio_chip gpio_chip;
154 struct regmap *map;
313};
314
315struct ocelot_pinctrl {
316 struct device *dev;
317 struct pinctrl_dev *pctl;
318 struct gpio_chip gpio_chip;
319 struct regmap *map;
155 void __iomem *pincfg;
320 struct regmap *pincfg;
156 struct pinctrl_desc *desc;
157 struct ocelot_pmx_func func[FUNC_MAX];
158 u8 stride;
159};
160
161#define LUTON_P(p, f0, f1) \
162static struct ocelot_pin_caps luton_pin_##p = { \
163 .pin = p, \

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671 SPARX5_PIN(58),
672 SPARX5_PIN(59),
673 SPARX5_PIN(60),
674 SPARX5_PIN(61),
675 SPARX5_PIN(62),
676 SPARX5_PIN(63),
677};
678
321 struct pinctrl_desc *desc;
322 struct ocelot_pmx_func func[FUNC_MAX];
323 u8 stride;
324};
325
326#define LUTON_P(p, f0, f1) \
327static struct ocelot_pin_caps luton_pin_##p = { \
328 .pin = p, \

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836 SPARX5_PIN(58),
837 SPARX5_PIN(59),
838 SPARX5_PIN(60),
839 SPARX5_PIN(61),
840 SPARX5_PIN(62),
841 SPARX5_PIN(63),
842};
843
844#define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \
845static struct ocelot_pin_caps lan966x_pin_##p = { \
846 .pin = p, \
847 .functions = { \
848 FUNC_##f0, FUNC_##f1, FUNC_##f2, \
849 FUNC_##f3 \
850 }, \
851 .a_functions = { \
852 FUNC_##f4, FUNC_##f5, FUNC_##f6, \
853 FUNC_##f7 \
854 }, \
855}
856
857/* Pinmuxing table taken from data sheet */
858/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */
859LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
860LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
861LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
862LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
863LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
864LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
865LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
866LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
867LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R);
868LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R);
869LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R);
870LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
871LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
872LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
873LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
874LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
875LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
876LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
877LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
878LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
879LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R);
880LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
881LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
882LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R);
883LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R);
884LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
885LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R);
886LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, NONE, R);
887LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
888LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
889LAN966X_P(30, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R);
890LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R);
891LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R);
892LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
893LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
894LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R);
895LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R);
896LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
897LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R);
898LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R);
899LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R);
900LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
901LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
902LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
903LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
904LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R);
905LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R);
906LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R);
907LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R);
908LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R);
909LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R);
910LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);
911LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R);
912LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);
913LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
914LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
915LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R);
916LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R);
917LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R);
918LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
919LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
920LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R);
921LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
922LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
923LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R);
924LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R);
925LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R);
926LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
927LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
928LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
929LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
930LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
931LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
932LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R);
933LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R);
934LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R);
935LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R);
936LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R);
937
938#define LAN966X_PIN(n) { \
939 .number = n, \
940 .name = "GPIO_"#n, \
941 .drv_data = &lan966x_pin_##n \
942}
943
944static const struct pinctrl_pin_desc lan966x_pins[] = {
945 LAN966X_PIN(0),
946 LAN966X_PIN(1),
947 LAN966X_PIN(2),
948 LAN966X_PIN(3),
949 LAN966X_PIN(4),
950 LAN966X_PIN(5),
951 LAN966X_PIN(6),
952 LAN966X_PIN(7),
953 LAN966X_PIN(8),
954 LAN966X_PIN(9),
955 LAN966X_PIN(10),
956 LAN966X_PIN(11),
957 LAN966X_PIN(12),
958 LAN966X_PIN(13),
959 LAN966X_PIN(14),
960 LAN966X_PIN(15),
961 LAN966X_PIN(16),
962 LAN966X_PIN(17),
963 LAN966X_PIN(18),
964 LAN966X_PIN(19),
965 LAN966X_PIN(20),
966 LAN966X_PIN(21),
967 LAN966X_PIN(22),
968 LAN966X_PIN(23),
969 LAN966X_PIN(24),
970 LAN966X_PIN(25),
971 LAN966X_PIN(26),
972 LAN966X_PIN(27),
973 LAN966X_PIN(28),
974 LAN966X_PIN(29),
975 LAN966X_PIN(30),
976 LAN966X_PIN(31),
977 LAN966X_PIN(32),
978 LAN966X_PIN(33),
979 LAN966X_PIN(34),
980 LAN966X_PIN(35),
981 LAN966X_PIN(36),
982 LAN966X_PIN(37),
983 LAN966X_PIN(38),
984 LAN966X_PIN(39),
985 LAN966X_PIN(40),
986 LAN966X_PIN(41),
987 LAN966X_PIN(42),
988 LAN966X_PIN(43),
989 LAN966X_PIN(44),
990 LAN966X_PIN(45),
991 LAN966X_PIN(46),
992 LAN966X_PIN(47),
993 LAN966X_PIN(48),
994 LAN966X_PIN(49),
995 LAN966X_PIN(50),
996 LAN966X_PIN(51),
997 LAN966X_PIN(52),
998 LAN966X_PIN(53),
999 LAN966X_PIN(54),
1000 LAN966X_PIN(55),
1001 LAN966X_PIN(56),
1002 LAN966X_PIN(57),
1003 LAN966X_PIN(58),
1004 LAN966X_PIN(59),
1005 LAN966X_PIN(60),
1006 LAN966X_PIN(61),
1007 LAN966X_PIN(62),
1008 LAN966X_PIN(63),
1009 LAN966X_PIN(64),
1010 LAN966X_PIN(65),
1011 LAN966X_PIN(66),
1012 LAN966X_PIN(67),
1013 LAN966X_PIN(68),
1014 LAN966X_PIN(69),
1015 LAN966X_PIN(70),
1016 LAN966X_PIN(71),
1017 LAN966X_PIN(72),
1018 LAN966X_PIN(73),
1019 LAN966X_PIN(74),
1020 LAN966X_PIN(75),
1021 LAN966X_PIN(76),
1022 LAN966X_PIN(77),
1023};
1024
679static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
680{
681 return ARRAY_SIZE(ocelot_function_names);
682}
683
684static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
685 unsigned int function)
686{

--- 17 unchanged lines hidden (view full) ---

704 unsigned int pin, unsigned int function)
705{
706 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
707 int i;
708
709 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
710 if (function == p->functions[i])
711 return i;
1025static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
1026{
1027 return ARRAY_SIZE(ocelot_function_names);
1028}
1029
1030static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
1031 unsigned int function)
1032{

--- 17 unchanged lines hidden (view full) ---

1050 unsigned int pin, unsigned int function)
1051{
1052 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
1053 int i;
1054
1055 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
1056 if (function == p->functions[i])
1057 return i;
1058
1059 if (function == p->a_functions[i])
1060 return i + OCELOT_FUNC_PER_PIN;
712 }
713
714 return -1;
715}
716
717#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
718
719static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,

--- 19 unchanged lines hidden (view full) ---

739 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
740 BIT(p), f << p);
741 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
742 BIT(p), f << (p - 1));
743
744 return 0;
745}
746
1061 }
1062
1063 return -1;
1064}
1065
1066#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
1067
1068static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,

--- 19 unchanged lines hidden (view full) ---

1088 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1089 BIT(p), f << p);
1090 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1091 BIT(p), f << (p - 1));
1092
1093 return 0;
1094}
1095
1096static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev,
1097 unsigned int selector, unsigned int group)
1098{
1099 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1100 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1101 unsigned int p = pin->pin % 32;
1102 int f;
1103
1104 f = ocelot_pin_function_idx(info, group, selector);
1105 if (f < 0)
1106 return -EINVAL;
1107
1108 /*
1109 * f is encoded on three bits.
1110 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1111 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2]
1112 * This is racy because three registers can't be updated at the same time
1113 * but it doesn't matter much for now.
1114 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets
1115 */
1116 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1117 BIT(p), f << p);
1118 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1119 BIT(p), (f >> 1) << p);
1120 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin),
1121 BIT(p), (f >> 2) << p);
1122
1123 return 0;
1124}
1125
747#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
748
749static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
750 struct pinctrl_gpio_range *range,
751 unsigned int pin, bool input)
752{
753 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
754 unsigned int p = pin % 32;

--- 14 unchanged lines hidden (view full) ---

769 regmap_update_bits(info->map, REG_ALT(0, info, offset),
770 BIT(p), 0);
771 regmap_update_bits(info->map, REG_ALT(1, info, offset),
772 BIT(p), 0);
773
774 return 0;
775}
776
1126#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
1127
1128static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
1129 struct pinctrl_gpio_range *range,
1130 unsigned int pin, bool input)
1131{
1132 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1133 unsigned int p = pin % 32;

--- 14 unchanged lines hidden (view full) ---

1148 regmap_update_bits(info->map, REG_ALT(0, info, offset),
1149 BIT(p), 0);
1150 regmap_update_bits(info->map, REG_ALT(1, info, offset),
1151 BIT(p), 0);
1152
1153 return 0;
1154}
1155
1156static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev,
1157 struct pinctrl_gpio_range *range,
1158 unsigned int offset)
1159{
1160 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1161 unsigned int p = offset % 32;
1162
1163 regmap_update_bits(info->map, REG_ALT(0, info, offset),
1164 BIT(p), 0);
1165 regmap_update_bits(info->map, REG_ALT(1, info, offset),
1166 BIT(p), 0);
1167 regmap_update_bits(info->map, REG_ALT(2, info, offset),
1168 BIT(p), 0);
1169
1170 return 0;
1171}
1172
777static const struct pinmux_ops ocelot_pmx_ops = {
778 .get_functions_count = ocelot_get_functions_count,
779 .get_function_name = ocelot_get_function_name,
780 .get_function_groups = ocelot_get_function_groups,
781 .set_mux = ocelot_pinmux_set_mux,
782 .gpio_set_direction = ocelot_gpio_set_direction,
783 .gpio_request_enable = ocelot_gpio_request_enable,
784};
785
1173static const struct pinmux_ops ocelot_pmx_ops = {
1174 .get_functions_count = ocelot_get_functions_count,
1175 .get_function_name = ocelot_get_function_name,
1176 .get_function_groups = ocelot_get_function_groups,
1177 .set_mux = ocelot_pinmux_set_mux,
1178 .gpio_set_direction = ocelot_gpio_set_direction,
1179 .gpio_request_enable = ocelot_gpio_request_enable,
1180};
1181
1182static const struct pinmux_ops lan966x_pmx_ops = {
1183 .get_functions_count = ocelot_get_functions_count,
1184 .get_function_name = ocelot_get_function_name,
1185 .get_function_groups = ocelot_get_function_groups,
1186 .set_mux = lan966x_pinmux_set_mux,
1187 .gpio_set_direction = ocelot_gpio_set_direction,
1188 .gpio_request_enable = lan966x_gpio_request_enable,
1189};
1190
786static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
787{
788 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
789
790 return info->desc->npins;
791}
792
793static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,

--- 20 unchanged lines hidden (view full) ---

814static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
815 unsigned int pin,
816 unsigned int reg,
817 int *val)
818{
819 int ret = -EOPNOTSUPP;
820
821 if (info->pincfg) {
1191static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1192{
1193 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1194
1195 return info->desc->npins;
1196}
1197
1198static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,

--- 20 unchanged lines hidden (view full) ---

1219static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
1220 unsigned int pin,
1221 unsigned int reg,
1222 int *val)
1223{
1224 int ret = -EOPNOTSUPP;
1225
1226 if (info->pincfg) {
822 u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
1227 u32 regcfg;
823
1228
1229 ret = regmap_read(info->pincfg, pin, &regcfg);
1230 if (ret)
1231 return ret;
1232
824 ret = 0;
825 switch (reg) {
826 case PINCONF_BIAS:
827 *val = regcfg & BIAS_BITS;
828 break;
829
830 case PINCONF_SCHMITT:
831 *val = regcfg & SCHMITT_BIT;

--- 6 unchanged lines hidden (view full) ---

838 default:
839 ret = -EOPNOTSUPP;
840 break;
841 }
842 }
843 return ret;
844}
845
1233 ret = 0;
1234 switch (reg) {
1235 case PINCONF_BIAS:
1236 *val = regcfg & BIAS_BITS;
1237 break;
1238
1239 case PINCONF_SCHMITT:
1240 *val = regcfg & SCHMITT_BIT;

--- 6 unchanged lines hidden (view full) ---

1247 default:
1248 ret = -EOPNOTSUPP;
1249 break;
1250 }
1251 }
1252 return ret;
1253}
1254
1255static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr,
1256 u32 clrbits, u32 setbits)
1257{
1258 u32 val;
1259 int ret;
1260
1261 ret = regmap_read(info->pincfg, regaddr, &val);
1262 if (ret)
1263 return ret;
1264
1265 val &= ~clrbits;
1266 val |= setbits;
1267
1268 ret = regmap_write(info->pincfg, regaddr, val);
1269
1270 return ret;
1271}
1272
846static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
847 unsigned int pin,
848 unsigned int reg,
849 int val)
850{
851 int ret = -EOPNOTSUPP;
852
853 if (info->pincfg) {
1273static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
1274 unsigned int pin,
1275 unsigned int reg,
1276 int val)
1277{
1278 int ret = -EOPNOTSUPP;
1279
1280 if (info->pincfg) {
854 void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
855
856 ret = 0;
857 switch (reg) {
858 case PINCONF_BIAS:
1281
1282 ret = 0;
1283 switch (reg) {
1284 case PINCONF_BIAS:
859 ocelot_clrsetbits(regaddr, BIAS_BITS, val);
1285 ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS,
1286 val);
860 break;
861
862 case PINCONF_SCHMITT:
1287 break;
1288
1289 case PINCONF_SCHMITT:
863 ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
1290 ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT,
1291 val);
864 break;
865
866 case PINCONF_DRIVE_STRENGTH:
867 if (val <= 3)
1292 break;
1293
1294 case PINCONF_DRIVE_STRENGTH:
1295 if (val <= 3)
868 ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
1296 ret = ocelot_pincfg_clrsetbits(info, pin,
1297 DRIVE_BITS, val);
869 else
870 ret = -EINVAL;
871 break;
872
873 default:
874 ret = -EOPNOTSUPP;
875 break;
876 }

--- 196 unchanged lines hidden (view full) ---

1073 .pins = sparx5_pins,
1074 .npins = ARRAY_SIZE(sparx5_pins),
1075 .pctlops = &ocelot_pctl_ops,
1076 .pmxops = &ocelot_pmx_ops,
1077 .confops = &ocelot_confops,
1078 .owner = THIS_MODULE,
1079};
1080
1298 else
1299 ret = -EINVAL;
1300 break;
1301
1302 default:
1303 ret = -EOPNOTSUPP;
1304 break;
1305 }

--- 196 unchanged lines hidden (view full) ---

1502 .pins = sparx5_pins,
1503 .npins = ARRAY_SIZE(sparx5_pins),
1504 .pctlops = &ocelot_pctl_ops,
1505 .pmxops = &ocelot_pmx_ops,
1506 .confops = &ocelot_confops,
1507 .owner = THIS_MODULE,
1508};
1509
1510static struct pinctrl_desc lan966x_desc = {
1511 .name = "lan966x-pinctrl",
1512 .pins = lan966x_pins,
1513 .npins = ARRAY_SIZE(lan966x_pins),
1514 .pctlops = &ocelot_pctl_ops,
1515 .pmxops = &lan966x_pmx_ops,
1516 .confops = &ocelot_confops,
1517 .owner = THIS_MODULE,
1518};
1519
1081static int ocelot_create_group_func_map(struct device *dev,
1082 struct ocelot_pinctrl *info)
1083{
1084 int f, npins, i;
1085 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
1086
1087 if (!pins)
1088 return -ENOMEM;

--- 214 unchanged lines hidden (view full) ---

1303 struct gpio_irq_chip *girq;
1304 int irq;
1305
1306 info->gpio_chip = ocelot_gpiolib_chip;
1307
1308 gc = &info->gpio_chip;
1309 gc->ngpio = info->desc->npins;
1310 gc->parent = &pdev->dev;
1520static int ocelot_create_group_func_map(struct device *dev,
1521 struct ocelot_pinctrl *info)
1522{
1523 int f, npins, i;
1524 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
1525
1526 if (!pins)
1527 return -ENOMEM;

--- 214 unchanged lines hidden (view full) ---

1742 struct gpio_irq_chip *girq;
1743 int irq;
1744
1745 info->gpio_chip = ocelot_gpiolib_chip;
1746
1747 gc = &info->gpio_chip;
1748 gc->ngpio = info->desc->npins;
1749 gc->parent = &pdev->dev;
1311 gc->base = 0;
1312 gc->of_node = info->dev->of_node;
1750 gc->base = -1;
1313 gc->label = "ocelot-gpio";
1314
1315 irq = irq_of_parse_and_map(gc->of_node, 0);
1316 if (irq) {
1317 girq = &gc->irq;
1318 girq->chip = &ocelot_irqchip;
1319 girq->parent_handler = ocelot_irq_handler;
1320 girq->num_parents = 1;

--- 11 unchanged lines hidden (view full) ---

1332}
1333
1334static const struct of_device_id ocelot_pinctrl_of_match[] = {
1335 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
1336 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
1337 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
1338 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
1339 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
1751 gc->label = "ocelot-gpio";
1752
1753 irq = irq_of_parse_and_map(gc->of_node, 0);
1754 if (irq) {
1755 girq = &gc->irq;
1756 girq->chip = &ocelot_irqchip;
1757 girq->parent_handler = ocelot_irq_handler;
1758 girq->num_parents = 1;

--- 11 unchanged lines hidden (view full) ---

1770}
1771
1772static const struct of_device_id ocelot_pinctrl_of_match[] = {
1773 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
1774 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
1775 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
1776 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
1777 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
1778 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
1340 {},
1341};
1342
1779 {},
1780};
1781
1782static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev)
1783{
1784 void __iomem *base;
1785
1786 const struct regmap_config regmap_config = {
1787 .reg_bits = 32,
1788 .val_bits = 32,
1789 .reg_stride = 4,
1790 .max_register = 32,
1791 };
1792
1793 base = devm_platform_ioremap_resource(pdev, 0);
1794 if (IS_ERR(base)) {
1795 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
1796 return NULL;
1797 }
1798
1799 return devm_regmap_init_mmio(&pdev->dev, base, &regmap_config);
1800}
1801
1343static int ocelot_pinctrl_probe(struct platform_device *pdev)
1344{
1345 struct device *dev = &pdev->dev;
1346 struct ocelot_pinctrl *info;
1802static int ocelot_pinctrl_probe(struct platform_device *pdev)
1803{
1804 struct device *dev = &pdev->dev;
1805 struct ocelot_pinctrl *info;
1806 struct regmap *pincfg;
1347 void __iomem *base;
1807 void __iomem *base;
1348 struct resource *res;
1349 int ret;
1350 struct regmap_config regmap_config = {
1351 .reg_bits = 32,
1352 .val_bits = 32,
1353 .reg_stride = 4,
1354 };
1355
1356 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);

--- 16 unchanged lines hidden (view full) ---

1373 dev_err(dev, "Failed to create regmap\n");
1374 return PTR_ERR(info->map);
1375 }
1376 dev_set_drvdata(dev, info->map);
1377 info->dev = dev;
1378
1379 /* Pinconf registers */
1380 if (info->desc->confops) {
1808 int ret;
1809 struct regmap_config regmap_config = {
1810 .reg_bits = 32,
1811 .val_bits = 32,
1812 .reg_stride = 4,
1813 };
1814
1815 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);

--- 16 unchanged lines hidden (view full) ---

1832 dev_err(dev, "Failed to create regmap\n");
1833 return PTR_ERR(info->map);
1834 }
1835 dev_set_drvdata(dev, info->map);
1836 info->dev = dev;
1837
1838 /* Pinconf registers */
1839 if (info->desc->confops) {
1381 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1382 base = devm_ioremap_resource(dev, res);
1383 if (IS_ERR(base))
1384 dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
1840 pincfg = ocelot_pinctrl_create_pincfg(pdev);
1841 if (IS_ERR(pincfg))
1842 dev_dbg(dev, "Failed to create pincfg regmap\n");
1385 else
1843 else
1386 info->pincfg = base;
1844 info->pincfg = pincfg;
1387 }
1388
1389 ret = ocelot_pinctrl_register(pdev, info);
1390 if (ret)
1391 return ret;
1392
1393 ret = ocelot_gpiochip_register(pdev, info);
1394 if (ret)

--- 16 unchanged lines hidden --- 		1845 }
1846
1847 ret = ocelot_pinctrl_register(pdev, info);
1848 if (ret)
1849 return ret;
1850
1851 ret = ocelot_gpiochip_register(pdev, info);
1852 if (ret)

--- 16 unchanged lines hidden ---